adc-dma.asm

blankfin 的 dma 驱动控制代码

	// IVG12 Handler (Programmable flag A/B)
    R0 = _I12HANDLER (Z);	
	R0.H = _I12HANDLER;		
    [ P0 ++ ] = R0;

	// IVG13 Handler (Memory DMA )
    R0 = _I13HANDLER (Z);	
	R0.H = _I13HANDLER;		
    [ P0 ++ ] = R0;

	// IVG14 Handler (Software Interrrupt 0)
    R0 = _I14HANDLER (Z);	
	R0.H = _I14HANDLER;		
    [ P0 ++ ] = R0;

	// IVG15 Handler (Software Interrupt 1)
    R0 = _I15HANDLER (Z);	
	R0.H = _I15HANDLER;		
    [ P0 ++ ] = R0;

	// ???????????
	P0 = EVT_OVERRIDE & 0xffff;
	P0.H = EVT_OVERRIDE >> 16;
    R0 = 0;
    [ P0 ] = R0;

	/*===================================*/
	rts;

/*-----------------------------------------/
	Setup all the interrupt handler 
/----------------------------------------*/
SetupCoreTimer:
	/* Setup core timer */
	i0.l = TCNTL & 0xffff;
	i0.h = TCNTL >> 16;	
	m0=4;
	r0=0x5 (Z);
	[i0++m0] = r0;		//Ctimer Control reg
	csync;

	r1.l=0x0000;
	r1.h=0x0004;
	[i0++m0]=r1;		//Ctimer period
	csync;
	
	r2 = 0x0080 (Z);
	[i0++m0]=r2;		//Ctimer scale
	csync;

	[i0]=r1;			//Ctimer count
	csync;
	
	rts;

	
/*----------------------------------------------*
 *	Name		:	SetupEBIUAsynchMem
 *	Function	:	Setup EBIU 's Aych memory for
 				  	ADC/DAC data
 *	Register 	:
 *		In:			None		
 *		Out:		None
 *		Used:									
 *	Author		:	Jeff Sondermeyer
 *  Create Date	:	01/11/2002
 *	Modified	:	
 *----------------------------------------------*/
SetupEBIUAsynchMem:
	p0.l = EBIU_AMBCTL0 & 0xffff;
	p0.h = (EBIU_AMBCTL0 >> 16) & 0xffff;
	
	// Bank 0: Ardy =0, ArdyPol =0,  BTT =01(1), BST =01(1), BHT =10 (2), BRAT =0001 (1), BWAT = 0100(4).
	r0.l = 0xffc7;	//0x4194;	
	
	//Keep Default value for bank 1												
	r0.h = 0xffc2; 	
	[p0] = r0;
	SSYNC;

	p0.l = EBIU_AMBCTL1 & 0xffff;
	p0.h = (EBIU_AMBCTL1 >> 16) & 0xffff;

	// Bank 2: Ardy =1, ArdyPol =1,  BTT =01(1), BST =00(3), BHT =11 (3), BRAT =1111 (15), BWAT = 1111(15).
	r0.l = 0xffc7;	
	
	//Keep Default value for bank 3												
	r0.h = 0xffc2; 	
	[p0] = r0;
	SSYNC;
														
	
	p0.l = EBIU_AMGCTL & 0xffff;		
	p0.h = (EBIU_AMGCTL >> 16) & 0xffff;

	//Clockout: Enabled, Bank0,1,2,3: enabled; 32 bits data path enabled
	r0 = 0x0007 (z);	
	W[p0] = r0;			
	SSYNC;				

	RTS;

/*----------------------------------------------*
 *	Name		:	InitCommonDMA
 *	Function	:	Initialize some common stuff for DMA.
 					For ex: DP BASE address, End DMA DP etc.
 *	Register 	:
 *		In:			None		
 *		Out:		None
 *		Used:									
 *	Author		:	Jeff Sondermeyer
 *  Create Date	:	01/11/2002
 *	Modified	:	
 *----------------------------------------------*/
InitCommonDMA:

	//Initialize RXDMA count and TX DMA count
	p0.l		= RXDMACount;
	p0.h		= RXDMACount;
    r0			= 0;
	[p0++]		= r0;	//RX
	[p0]		= r0;	//TX

	//Init ending dp, all DMA DP point to this after transaction;
	p0.l	= DMAEndDp;
	p0.h	= DMAEndDp;
	r0.l	= 0;
	W[p0]	= r0.l;

	//Init Descriptor base pointer register */
	r0.l	= RXReadDMADp1;
	r0.h	= RXReadDMADp1;
	P0.L 	= DB_NDBP & 0xFFFF;
	P0.H 	= (DB_NDBP >> 16) & 0xFFFF;	
	W[p0]	= r0.h;

	RTS;

/*----------------------------------------------*
 *	Name		:	SetupRXDMA
 *	Function	:	Setup RX MemDMA for get data
 					From ADC
 *	Register 	:
 *		In:			None		
 *		Out:		None
 *		Used:									
 *	Author		:	Jeff Sondermeyer
 *  Create Date	:	01/11/2002
 *	Modified	:	
 *----------------------------------------------*/
SetupRXDMA:

	/* Source DMA */	
	//Read Descripter1 Setup
	p0.l		= RXReadDMADp1;
	p0.h		= RXReadDMADp1;

	//Configuration, 32bit, int disable
	r0.l		= 0x8009;		
	W[p0]		= r0.l;
	r0.l		= RX_DMA_LENGTH_SOURCE;
	W[p0+0x2]	= r0;
	r0.l		= IO_PORT_ADDR  & 0xffff;
	r0.h		= (IO_PORT_ADDR >> 16) & 0xffff;
	[p0+0x4]	= r0;
	r0.l		= RXReadDMADp2;
	W[p0+0x8]	= r0;

	//Setup Next DP pointer
	r0		= p0;
	P0.L 	= MDR_DND & 0xFFFF;
	P0.H 	= (MDR_DND >> 16) & 0xFFFF;	
	W[p0]	= r0.l;

	//Read Descripter2 Setup
	p0.l		= RXReadDMADp2;
	p0.h		= RXReadDMADp2;

	//Configuration, 32bit, int disable
	r0.l		= 0x8009;
	W[p0]		= r0.l;
	r0.l		= RX_DMA_LENGTH_SOURCE;
	W[p0+0x2]	= r0;
	r0.l		= IO_PORT_ADDR & 0xffff;
	r0.h		= (IO_PORT_ADDR >> 16) & 0xffff;
	[p0+0x4]	= r0;
	r0.l		= RXReadDMADp1;
	W[p0+0x8]	= r0;

	/* Destination DMA */
	// Write descriptor1 Setup 
	p0.l		= RXWriteDMADp1;
	p0.h		= RXWriteDMADp1;

	//Configuration, 32bit, int enabled on completion
	r0.l		= 0x800b;
	W[p0]		= r0.l;
	r0.l		= RX_DMA_LENGTH_DESTINATION;
	W[p0+0x2]	= r0;
	r0.l		= RXDMABufferA;
	r0.h		= RXDMABufferA;
	[p0+0x4]	= r0;
	r0.l		= RXWriteDMADp2;
	W[p0+0x8]	= r0;

	//Setup Next DP pointer
	r0		= p0;
	P0.L 	= MDW_DND & 0xFFFF;
	P0.H 	= (MDW_DND >> 16) & 0xFFFF;	
	W[p0]	= r0.l;

	// Write descriptor2 Setup 
	p0.l		= RXWriteDMADp2;
	p0.h		= RXWriteDMADp2;

	//Configuration, 32bit, int enabled on completion
	r0.l		= 0x800b;
	W[p0]		= r0.l;
	r0.l		= RX_DMA_LENGTH_DESTINATION;
	W[p0+0x2]	= r0;
	r0.l		= RXDMABufferB;
	r0.h		= RXDMABufferB;
	[p0+0x4]	= r0;
	r0.l		= RXWriteDMADp1;
	W[p0+0x8]	= r0;

	RTS;

/*----------------------------------------------*
 *	Name		:	StartRXDMA
 *	Function	:	Start RX MemDMA for get data
 					From ADC
 *	Register 	:
 *		In:			None		
 *		Out:		None
 *		Used:									
 *	Author		:	Jeff Sondermeyer
 *  Create Date	:	01/11/2002
 *	Modified	:	
 *----------------------------------------------*/

StartRXDMA:
	// Enable Destination
	P0.L 	= MDW_DCFG & 0xFFFF;
	P0.H 	= (MDW_DCFG >> 16) & 0xFFFF;	
	R0 		= W[P0];
	BITSET(R0,0);
	W[p0]	= R0.l;

	// Enable source
	P0.L 	= MDR_DCFG & 0xFFFF;
	P0.H 	= (MDR_DCFG >> 16) & 0xFFFF;	
	R0 		= W[P0];
	BITSET(R0,0);
	W[p0]	= r0.l;
	RTS;

/*----------------------------------------------*
 *	Name		:	SetupTXDMA
 *	Function	:	Setup TX MemDMA to send data
 					to DAC
 *	Register 	:
 *		In:			None		
 *		Out:		None
 *		Used:									
 *	Author		:	Jeff Sondermeyer
 *  Create Date	:	01/17/2002
 *	Modified	:	
 *----------------------------------------------*/
SetupTXDMA:

	/* Source DMA */	
	//Read Descripter1 Setup
	p0.l		= TXReadDMADp1;
	p0.h		= TXReadDMADp1;

	//Configuration, 32bit, int disable
	r0.l		= 0x8009;		
	W[p0]		= r0.l;
	r0.l		= TX_DMA_LENGTH_SOURCE;
	W[p0+0x2]	= r0;
	r0.l		= TXDMABufferA;
	r0.h		= TXDMABufferA;
	[p0+0x4]	= r0;
	r0.l		= TXReadDMADp2;
	W[p0+0x8]	= r0;

	//Setup Next DP pointer
	r0		= p0;
	P0.L 	= MDR_DND & 0xFFFF;
	P0.H 	= (MDR_DND >> 16) & 0xFFFF;	
	W[p0]	= r0.l;

	//Read Descripter2 Setup
	p0.l		= TXReadDMADp2;
	p0.h		= TXReadDMADp2;

	//Configuration, 32bit, int disable
	r0.l		= 0x8009;
	W[p0]		= r0.l;
	r0.l		= TX_DMA_LENGTH_SOURCE;
	W[p0+0x2]	= r0;
	r0.l		= TXDMABufferB;
	r0.h		= TXDMABufferB;
	[p0+0x4]	= r0;
	r0.l		= TXReadDMADp1;
	W[p0+0x8]	= r0;

	/* Destination DMA */
	// Write descriptor1 Setup 
	p0.l		= TXWriteDMADp1;
	p0.h		= TXWriteDMADp1;

	//Configuration, 32bit, int enabled on completion
	r0.l		= 0x800f;
	W[p0]		= r0.l;
	r0.l		= TX_DMA_LENGTH_DESTINATION;
	W[p0+0x2]	= r0;
	r0.l		= IO_PORT_ADDR  & 0xffff;
	r0.h		= (IO_PORT_ADDR >> 16) & 0xffff;
	[p0+0x4]	= r0;
	r0.l		= TXWriteDMADp2;
	W[p0+0x8]	= r0;

	//Setup Next DP pointer
	r0		= p0;
	P0.L 	= MDW_DND & 0xFFFF;
	P0.H 	= (MDW_DND >> 16) & 0xFFFF;	
	W[p0]	= r0.l;

	// Write descriptor2 Setup 
	p0.l		= TXWriteDMADp2;
	p0.h		= TXWriteDMADp2;

	//Configuration, 32bit, int enabled on completion
	r0.l		= 0x800f;
	W[p0]		= r0.l;
	r0.l		= TX_DMA_LENGTH_DESTINATION;
	W[p0+0x2]	= r0;
	r0.l		= IO_PORT_ADDR & 0xffff;
	r0.h		= (IO_PORT_ADDR >> 16) & 0xffff;
	[p0+0x4]	= r0;
	r0.l		= TXWriteDMADp1;
	W[p0+0x8]	= r0;

	RTS;

/*----------------------------------------------*
 *	Name		:	StartTXDMA
 *	Function	:	Start TX MemDMA to send data to DA
 *	Register 	:
 *		In:			None		
 *		Out:		None
 *		Used:									
 *	Author		:	Jeff Sondermeyer
 *  Create Date	:	01/11/2002
 *	Modified	:	
 *----------------------------------------------*/

StartTXDMA:
	// Enable Dest
	P0.L 	= MDW_DCFG & 0xFFFF;
	P0.H 	= (MDW_DCFG >> 16) & 0xFFFF;	
	R0 		= W[P0];
	BITSET(R0,0);
	W[p0]	= R0.l;

	// Enable source
	P0.L 	= MDR_DCFG & 0xFFFF;
	P0.H 	= (MDR_DCFG >> 16) & 0xFFFF;	
	R0 		= W[P0];
	BITSET(R0,0);
	W[p0]	= r0.l;
	RTS;


	
/*SSSSSSSSSSSSSSSSSSSSSSSSSSSSSSSSSS*/
/*Start code Section*/
.section start_from_here;
	r0		= SetupOpMode(Z);
	r0.h	= SetupOpMode;
	p0		= r0;
	csync;
	jump	 (p0);
	nop;
	nop;

/*SSSSSSSSSSSSSSSSSSSSSSSSSSSSSSSSSS*/
/*Stack  Section*/
.section ustack;   
.align 4;
.var UserStackSpace0[1000];
UserStack:
.var UserStackSpace1[4];

/*SSSSSSSSSSSSSSSSSSSSSSSSSSSSSSSSSS*/
/*Data Section*/

// L2 bank 2 */
.section L2_B2_data;
/* MemDMA descriptor buffer */
//First RX 
.align 4;
.BYTE2	RXReadDMADp1[5];
.align 4;
.BYTE2	RXWriteDMADp1[5];

//First TX
.align 4;
.BYTE2	TXReadDMADp1[5];
.align 4;
.BYTE2	TXWriteDMADp1[5];


//END
.align 4;
.BYTE2	DMAEndDp[1];
.BYTE2	TimerToggle[1];
.align 4;
.BYTE4	RXDMACount[1];
.BYTE4	TXDMACount[1];
.align 4;
.BYTE2	SysMode[1];

// L2 Bank 3 */
.section L2_B3_data;
/* MemDMA descriptor buffer */
//Second RX
.align 4;
.BYTE2	RXReadDMADp2[5];
.align 4;
.BYTE2	RXWriteDMADp2[5];

//Second TX
.align 4;
.BYTE2	TXReadDMADp2[5];
.align 4;
.BYTE2	TXWriteDMADp2[5];


// L1 B bank, sub bank 0 */
.section L1_B0_data;
.align 4;
TXDMABufferA:
.BYTE4	RXDMABufferA[1024];

// L1 B bank, sub bank 1 */
.section L1_B1_data;
.align 4;
TXDMABufferB:
.BYTE4	RXDMABufferB[1024];