📄 adc-dma.asm
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#include <defBF535.h>
#define RX_DMA_LENGTH_SOURCE 65535
#define RX_DMA_LENGTH_DESTINATION 1023
#define TX_DMA_LENGTH_SOURCE 1023
#define TX_DMA_LENGTH_DESTINATION 65535
#define RX_MODE 1
#define TX_MODE 2
#define PR_MODE 4
#define PT_MODE 8
#define IO_PORT_ADDR 0x28000000 //Bank2 od asych mem, AMS2 effective
/*SSSSSSSSSSSSSSSSSSSSSSSSSSSSSSSSSS*/
/*Program Section*/
.section program;
/* Init operating mode, stay in supervisor */
SetupOpMode:
/* int 15 point to user program */
p0.l = EVT15 & 0xffff;
p0.h = (EVT15 >> 16) & 0xffff;
r0 = MainProc(Z);
r0.h = MainProc;
[p0] = r0;
/* Enable int 15 */
p0.l = IMASK & 0xffff;
p0.h = (IMASK >>16) & 0xffff;
r0.l = W[p0];
r1.l = EVT_IVG15;
r0 = r0 | r1;
W[p0] = r0.l;
/* Create int 15 */
raise 15;
p0.l = DeadLoop;
p0.h = DeadLoop;
reti = p0;
rti;
nop;
nop;
DeadLoop:
nop;
jump DeadLoop;
MainProc:
call InitRegs;
/* Initialize Stack */
SP =UserStack (Z);
SP.h =UserStack;
/* Enable interrupt,still in superviser mode */
[--sp] =reti;
call SetupEvtHandler;
call SetupCoreTimer;
/* Setup EBIU */
call SetupEBIUAsynchMem;
/* Init Mode as TX, 0-RX, 1-TX, 2-PR, 3-PT */
p0.l = SysMode;
p0.h = SysMode;
r0.l = RX_MODE;
W[p0] = r0.l;
/* Setup DMA */
call InitCommonDMA;
call SetupRXDMA;
/* Setup PF pin, PF0,1,2,3 output */
r0.l=0x000f;
p0.l = FIO_DIR & 0xffff;
p0.h = FIO_DIR >> 16;
p1.l = FIO_FLAG_S & 0xffff;
p1.h = FIO_FLAG_S >> 16;
p2.l = FIO_FLAG_C & 0xffff;
p2.h = FIO_FLAG_C >> 16;
W[p0] = r0;
/* Enable MemDMA sys int . Manual has something wrong, it is clear to enable interrupt*/
i1.L = SIC_IMASK & 0xffff;
i1.H = SIC_IMASK >> 16;
r3 = [i1];
bitclr(r3, 19);
[i1] = r3;
csync;
/* Enable core timer interrupt & MemDMA write int */
i1.L = IMASK & 0xffff;
i1.H = IMASK >> 16;
r3 = 0x2040 (Z);
[ i1 ] = r3;
csync;
/* Start RX DMA operation */
call StartRXDMA;
/* Start core timer */
i0.l = TCNTL & 0xffff;
i0.h = TCNTL >> 16;
r4 = 0x0007 (Z);
r5=0x1;
/* Testing DMA */
LoopA:
p1.l = RXReadDMADp1;
p1.h = RXReadDMADp1;
DMA_WAIT1:
R6 = W[P1];
cc = bittst(R6,15);
IF cc JUMP DMA_WAIT1;
nop;
bitset(r6,15);
W[p1] = R6;
nop;
p1.l = RXWriteDMADp1;
p1.h = RXWriteDMADp1;
R6 = W[P1];
bitset(r6,15);
W[p1] = R6;
nop;
p1.l = RXReadDMADp2;
p1.h = RXReadDMADp2;
DMA_WAIT2:
R6 = W[P1];
cc = bittst(R6,15);
IF cc JUMP DMA_WAIT2;
nop;
bitset(r6,15);
W[p1] = R6;
nop;
nop;
p1.l = RXWriteDMADp2;
p1.h = RXWriteDMADp2;
R6 = W[P1];
bitset(r6,15);
W[p1] = R6;
nop;
jump LoopA;
_EHANDLER: // Emulation Handler 0
RTE;
_RHANDLER: // Reset Handler 1
RTI;
_NHANDLER: // NMI Handler 2
RTN;
_XHANDLER: // Exception Handler 3
off1:
nop;
nop;
Jump off1;
RTX;
_HWHANDLER: // HW Error Handler 5
off2:
nop;
nop;
Jump off2;
RTI;
_THANDLER: // Timer Handler 6
[--sp] = p1;
[--sp] = p2;
[--sp] = r5;
p1.l = FIO_FLAG_S & 0xffff;
p1.h = FIO_FLAG_S >> 16;
p2.l = TimerToggle ;
p2.h = TimerToggle ;
r5 = W[p2](Z);
bittgl(r5,0);
W[p2] =r5.l;
CC = r5 == 0x1;
IF CC JUMP on;
p1.l = FIO_FLAG_C & 0xffff;
p1.h = FIO_FLAG_C >> 16;
on:
r5 = 0x0001;
W[p1]=r5;
r5 = [sp ++];
p2 = [sp ++];
p1 = [sp ++];
RTI;
_RTCHANDLER: // IVG 7 Handler (RTC)
RTI;
_I8HANDLER: // IVG 8 Handler
RTI;
_I9HANDLER: // IVG 9 Handler
RTI;
_I10HANDLER: // IVG 10 Handler
RTI;
_I11HANDLER: // IVG 11 Handler
RTI;
_I12HANDLER: // IVG 12 Handler
RTI;
_I13HANDLER: // IVG 13 Handler
[--sp] = p0;
[--sp] = r0;
[--sp] = r1;
/* Clear MemWDMA interrupt reg */
p0.l = MDR_DI & 0xffff;
p0.h = (MDR_DI >> 16) & 0xffff;
r0.l = W[p0];
W[p0] = r0.l;
/*=======*/
p0.l = SysMode;
p0.h = SysMode;
r0.l = W[p0];
cc= bittst(r0, 1);
if cc Jump TXProcessing;
RXProcessing:
p0.l = RXDMACount;
p0.h = RXDMACount;
r0 = [p0];
r0 += 1;
[p0] = r0;
p0.l = FIO_FLAG_C & 0xffff;
p0.h = FIO_FLAG_C >> 16;
cc = bittst(r0,22);
if cc jump RXLedOff;
p0.l = FIO_FLAG_S & 0xffff;
p0.h = FIO_FLAG_S >> 16;
RXLedOff:
r1 = 0x0002;
W[p0] = r1;
cc = bittst(r0,0);
if cc jump RXOddFrame;
p0.l = RXReadDMADp2;
p0.h = RXReadDMADp2;
r0 = W[p0];
bitset(r0,15);
W[p0] = r0;
p0.l = RXWriteDMADp2;
p0.h = RXWriteDMADp2;
r0 = W[p0];
bitset(r0,15);
W[p0] = r0;
jump MemDMAISREnd;
RXOddFrame:
p0.l = RXReadDMADp1;
p0.h = RXReadDMADp1;
r0 = W[p0];
bitset(r0,15);
W[p0] = r0;
p0.l = RXWriteDMADp1;
p0.h = RXWriteDMADp1;
r0 = W[p0];
bitset(r0,15);
W[p0] = r0;
MemDMAISREnd:
r1 = [sp++];
r0 = [sp++];
p0 = [sp++];
rti;
TXProcessing:
p0.l = TXDMACount;
p0.h = TXDMACount;
r0 = [p0];
r0 += 1;
[p0] = r0;
p0.l = FIO_FLAG_C & 0xffff;
p0.h = FIO_FLAG_C >> 16;
cc = bittst(r0,22);
if cc jump TXLedOff;
p0.l = FIO_FLAG_S & 0xffff;
p0.h = FIO_FLAG_S >> 16;
TXLedOff:
r1 = 0x0004;
W[p0] = r1;
cc = bittst(r0,0);
if cc jump TXOddFrame;
p0.l = TXReadDMADp2;
p0.h = TXReadDMADp2;
r0 = W[p0];
bitset(r0,15);
W[p0] = r0;
p0.l = TXWriteDMADp2;
p0.h = TXWriteDMADp2;
r0 = W[p0];
bitset(r0,15);
W[p0] = r0;
jump MemDMAISREnd;
TXOddFrame:
p0.l = TXReadDMADp1;
p0.h = TXReadDMADp1;
r0 = W[p0];
bitset(r0,15);
W[p0] = r0;
p0.l = TXWriteDMADp1;
p0.h = TXWriteDMADp1;
r0 = W[p0];
bitset(r0,15);
W[p0] = r0;
Jump MemDMAISREnd;
_I14HANDLER:
RTI;
_I15HANDLER:
RTI;
/////////////////////
/* Subroutine area */
/////////////////////
/*-----------------------------------------/
Init all register
Because the reset might not reset
the register into a legal value
/----------------------------------------*/
InitRegs:
/* Initialize all register file */
R0 = 0; R1 = 0; R2 = 0; R3 = 0;
R4 = 0; R5 = 0; R6 = 0; R7 = 0;
P0 = 0; P1 = 0; P2 = 0; P3 = 0; P4 = 0; P5 = 0;
I0 = 0 (X); I1 = 0 (X); I2 = 0 (X); I3 = 0 (X);
M0 = 0 (X); M1 = 0 (X); M2 = 0 (X); M3 = 0 (X);
L0 = 0 (X); L1 = 0 (X); L2 = 0 (X); L3 = 0 (X);
B0 = 0 (X); B1 = 0 (X); B2 = 0 (X); B3 = 0 (X);
rts;
/*-----------------------------------------/
Setup all the interrupt handler
/----------------------------------------*/
SetupEvtHandler:
/*===================================*/
/* Setup Event Vectors and Handlers */
R0 = 0;
p0.l = EVT0 & 0xffff;
p0.h = EVT0 >> 16;
p0 +=4;
// Reset Handler (Int1)
R0 = _RHANDLER (Z);
R0.H = _RHANDLER;
[ P0 ++ ] = R0;
// NMI Handler (Int2)
R0 = _NHANDLER (Z);
R0.H = _NHANDLER;
[ P0 ++ ] = R0;
// Exception Handler (Int3)
R0.L = _XHANDLER;
R0.H = _XHANDLER;
[ P0 ++ ] = R0;
// IVT4 isn't used, Reserved
[ P0 ++ ] = R0;
// HW Error Handler (Int5)
R0 = _HWHANDLER (Z);
R0.H = _HWHANDLER;
[ P0 ++ ] = R0;
// Core Timer Handler (Int6)
R0 = _THANDLER (Z);
R0.H = _THANDLER;
[ P0 ++ ] = R0;
// IVG7 Handler, (RTC, USB, PCI)
R0 = _RTCHANDLER (Z);
R0.H = _RTCHANDLER;
[ P0 ++ ] = R0;
// IVG8 Handler (SPORT0,1-RX/TX )
R0 = _I8HANDLER (Z);
R0.H = _I8HANDLER;
[ P0 ++ ] = R0;
// IVG9 Handler (SPI0,1)
R0 = _I9HANDLER (Z);
R0.H = _I9HANDLER;
[ P0 ++ ] = R0;
// IVG10 Handler (UART0,1 --RX/TX )
R0 = _I10HANDLER (Z);
R0.H = _I10HANDLER;
[ P0 ++ ] = R0;
// IVG11 Handler (Timer 0,1,2)
R0 = _I11HANDLER (Z);
R0.H = _I11HANDLER;
[ P0 ++ ] = R0;
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