📄 def21535.h
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#define PCI_DIBARM 0xEEFFFF04 // PCI Device IO Bar Mask
#define PCI_CFG_DIC 0xEEFFFF08 // PCI Config Device ID
#define PCI_CFG_VIC 0xEEFFFF0C // PCI Config Vendor ID
#define PCI_CFG_STAT 0xEEFFFF10 // PCI Config Status (Read-only)
#define PCI_CFG_CMD 0xEEFFFF14 // PCI Config Command
#define PCI_CFG_CC 0xEEFFFF18 // PCI Config Class Code
#define PCI_CFG_RID 0xEEFFFF1C // PCI Config Revision ID
#define PCI_CFG_BIST 0xEEFFFF20 // PCI Config BIST
#define PCI_CFG_HT 0xEEFFFF24 // PCI Config Header Type
#define PCI_CFG_MLT 0xEEFFFF28 // PCI Config Memory Latency Timer
#define PCI_CFG_CLS 0xEEFFFF2C // PCI Config Cache Line Size
#define PCI_CFG_MBAR 0xEEFFFF30 // PCI Config Memory Base Address Register
#define PCI_CFG_IBAR 0xEEFFFF34 // PCI Config IO Base Address Register
#define PCI_CFG_SID 0xEEFFFF38 // PCI Config Sub-system ID
#define PCI_CFG_SVID 0xEEFFFF3C // PCI Config Sub-system Vendor ID
#define PCI_CFG_MAXL 0xEEFFFF40 // PCI Config Maximum Latency Cycles
#define PCI_CFG_MING 0xEEFFFF44 // PCI Config Minimum Grant Cycles
#define PCI_CFG_IP 0xEEFFFF48 // PCI Config Interrupt Pin
#define PCI_CFG_IL 0xEEFFFF4C // PCI Config Interrupt Line
#define PCI_HMCTL 0xEEFFFF50 // PCI Blocking BAR Host Mode Control
// USB Registers (0xFFC0 4400 - 0xFFC0 47FF)
#define USBD_ID 0xFFC04400 // USB Device ID Register
#define USBD_FRM 0xFFC04402 // Current USB Frame Number
#define USBD_FRMAT 0xFFC04404 // Match value for USB frame number.
#define USBD_EPBUF 0xFFC04406 // Enables Download of Configuration Into UDC Core
#define USBD_STAT 0xFFC04408 // Returns USBD Module Status
#define USBD_CTRL 0xFFC0440A // Allows Configuration and Control of USBD Module.
#define USBD_GINTR 0xFFC0440C // Global Interrupt Register
#define USBD_GMASK 0xFFC0440E // Global Interrupt Register Mask
#define USBD_DMACFG 0xFFC04440 // DMA Master Channel Configuration Register
#define USBD_DMABL 0xFFC04442 // DMA Master Channel Base Address, Low
#define USBD_DMABH 0xFFC04444 // DMA Master Channel Base Address, High
#define USBD_DMACT 0xFFC04446 // DMA Master Channel Count Register
#define USBD_DMAIRQ 0xFFC04448 // DMA Master Channel DMA Count Register
#define USBD_INTR0 0xFFC04480 // USB Endpoint 0 Interrupt Register
#define USBD_MASK0 0xFFC04482 // USB Endpoint 0 Mask Register
#define USBD_EPCFG0 0xFFC04484 // USB Endpoint 0 Control Register
#define USBD_EPADR0 0xFFC04486 // USB Endpoint 0 Address Offset Register
#define USBD_EPLEN0 0xFFC04488 // USB Endpoint 0 Buffer Length Register
#define USBD_INTR1 0xFFC0448A // USB Endpoint 1 Interrupt Register
#define USBD_MASK1 0xFFC0448C // USB Endpoint 1 Mask Register
#define USBD_EPCFG1 0xFFC0448E // USB Endpoint 1 Control Register
#define USBD_EPADR1 0xFFC04490 // USB Endpoint 1 Address Offset Register
#define USBD_EPLEN1 0xFFC04492 // USB Endpoint 1 Buffer Length Register
#define USBD_INTR2 0xFFC04494 // USB Endpoint 2 Interrupt Register
#define USBD_MASK2 0xFFC04496 // USB Endpoint 2 Mask Register
#define USBD_EPCFG2 0xFFC04498 // USB Endpoint 2 Control Register
#define USBD_EPADR2 0xFFC0449A // USB Endpoint 2 Address Offset Register
#define USBD_EPLEN2 0xFFC0449C // USB Endpoint 2 Buffer Length Register
#define USBD_INTR3 0xFFC0449E // USB Endpoint 3 Interrupt Register
#define USBD_MASK3 0xFFC044A0 // USB Endpoint 3 Mask Register
#define USBD_EPCFG3 0xFFC044A2 // USB Endpoint 3 Control Register
#define USBD_EPADR3 0xFFC044A4 // USB Endpoint 3 Address Offset Register
#define USBD_EPLEN3 0xFFC044A6 // USB Endpoint 3 Buffer Length Register
#define USBD_INTR4 0xFFC044A8 // USB Endpoint 4 Interrupt Register
#define USBD_MASK4 0xFFC044AA // USB Endpoint 4 Mask Register
#define USBD_EPCFG4 0xFFC044AC // USB Endpoint 4 Control Register
#define USBD_EPADR4 0xFFC044AE // USB Endpoint 4 Address Offset Register
#define USBD_EPLEN4 0xFFC044B0 // USB Endpoint 4 Buffer Length Register
#define USBD_INTR5 0xFFC044B2 // USB Endpoint 5 Interrupt Register
#define USBD_MASK5 0xFFC044B4 // USB Endpoint 5 Mask Register
#define USBD_EPCFG5 0xFFC044B6 // USB Endpoint 5 Control Register
#define USBD_EPADR5 0xFFC044B8 // USB Endpoint 5 Address Offset Register
#define USBD_EPLEN5 0xFFC044BA // USB Endpoint 5 Buffer Length Register
#define USBD_INTR6 0xFFC044BC // USB Endpoint 6 Interrupt Register
#define USBD_MASK6 0xFFC044BE // USB Endpoint 6 Mask Register
#define USBD_EPCFG6 0xFFC044C0 // USB Endpoint 6 Control Register
#define USBD_EPADR6 0xFFC044C2 // USB Endpoint 6 Address Offset Register
#define USBD_EPLEN6 0xFFC044C4 // USB Endpoint 6 Buffer Length Register
#define USBD_INTR7 0xFFC044C6 // USB Endpoint 7 Interrupt Register
#define USBD_MASK7 0xFFC044C8 // USB Endpoint 7 Mask Register
#define USBD_EPCFG7 0xFFC044CA // USB Endpoint 7 Control Register
#define USBD_EPADR7 0xFFC044CC // USB Endpoint 7 Address Offset Register
#define USBD_EPLEN7 0xFFC044CE // USB Endpoint 7 Buffer Length Register
// System Bus Interface Unit (0xFFC0 4800-0xFFC0 4FFF)
#define L1SBAR 0xFFC04840 // L1 SRAM Base Address Register
#define L1CSR 0xFFC04844 // L1 SRAM Control Initialization Register
#define DB_NDBP 0xFFC04880 // Next Descriptor Base Pointer
#define DB_ACOMP 0xFFC04884 // DMA Bus Address Comparator
#define DB_CCOMP 0xFFC04888 // DMA Bus Control Comparator
// SDRAM Controller External Bus Interface Unit (0xFFC0 4C00-0xFFC0 4FFF)
#define EBIU_SDGCTL 0xFFC04C00 // SDRAM Global Control Register
#define EBIU_SDBCTL 0xFFC04C04 // SDRAM Bank Control Register
#define EBIU_SDRRC 0xFFC04C0A // SDRAM Refresh Rate Control Register
#define EBIU_SDSTAT 0xFFC04C0E // SDRAM Status Register
// PAB Reserved (0xFFC0 5000-0xFFDF FFFF) (**Reserved**)
//**********************************************************************************
// System MMR Register Bits
//**********************************************************************************
// PLLCTL Masks
#define PLL_CLKIN 0x00000000 // Pass CLKIN to PLL
#define PLL_CLKIN_DIV2 0x00000001 // Pass CLKIN/2 to PLL
#define PLL_OFF 0x00000002 // Shut off PLL clocks
#define STOPCK_OFF 0x00000008 // Core clock off
#define PDWN 0x00000020 // Put the PLL in a Deep Sleep state
#define BYPASS 0x00000100 // Bypass the PLL
#define CCLK_DIV2 0x00000000 // SCLK = CCLK / 2
#define CCLK_DIV2_5 0x00010000 // SCLK = CCLK / 2.5
#define CCLK_DIV3 0x00020000 // SCLK = CCLK / 3
#define CCLK_DIV4 0x00030000 // SCLK = CCLK / 4
// IOCKR Masks
#define IOCK_PCI 0x00000001 // Enable PCI peripheral clock
#define IOCK_L2 0x00000002 // Enable L2 memory peripheral clock
#define IOCK_EBIU 0x00000004 // Enable EBIU controller peripheral clock
#define IOCK_GPIO 0x00000008 // Enable GPIO peripheral clock
#define IOCK_MEMDMA 0x00000010 // Enable MemDMA controller peripheral clock
#define IOCK_SPORT0 0x00000020 // Enable SPORT0 controller peripheral clock
#define IOCK_SPORT1 0x00000040 // Enable SPORT1 controller peripheral clock
#define IOCK_SPI0 0x00000080 // Enable SPI0 controller peripheral clock
#define IOCK_SPI1 0x00000100 // Enable SPI1 controller peripheral clock
#define IOCK_UART0 0x00000200 // Enable UART0 controller peripheral clock
#define IOCK_UART1 0x00000400 // Enable UART1 controller peripheral clock
#define IOCK_TIMER0 0x00000800 // Enable TIMER0 peripheral clock
#define IOCK_TIMER1 0x00001000 // Enable TIMER1 peripheral clock
#define IOCK_TIMER2 0x00002000 // Enable TIMER2 peripheral clock
#define IOCK_USB 0x00004000 // Enable USB peripheral clock
// SWRST Mask
#define SYSTEM_RESET 0x00000007 // Initiates a system software reset
// System Interrupt Controller Masks (SIC_IAR0, SIC_IAR1, SIC_IAR2, SIC_IMASK, SIC_IWR)
// SIC_IAR0 Masks
//
#define P0_IVG7 0x00000000 // Peripheral #0 assigned IVG7
#define P0_IVG8 0x00000001 // Peripheral #0 assigned IVG8
#define P0_IVG9 0x00000002 // Peripheral #0 assigned IVG9
#define P0_IVG10 0x00000003 // Peripheral #0 assigned IVG10
#define P0_IVG11 0x00000004 // Peripheral #0 assigned IVG11
#define P0_IVG12 0x00000005 // Peripheral #0 assigned IVG12
#define P0_IVG13 0x00000006 // Peripheral #0 assigned IVG13
#define P0_IVG14 0x00000007 // Peripheral #0 assigned IVG14
#define P0_IVG15 0x00000008 // Peripheral #0 assigned IVG15
#define P1_IVG7 0x00000000 // Peripheral #1 assigned IVG7
#define P1_IVG8 0x00000010 // Peripheral #1 assigned IVG8
#define P1_IVG9 0x00000020 // Peripheral #1 assigned IVG9
#define P1_IVG10 0x00000030 // Peripheral #1 assigned IVG10
#define P1_IVG11 0x00000040 // Peripheral #1 assigned IVG11
#define P1_IVG12 0x00000050 // Peripheral #1 assigned IVG12
#define P1_IVG13 0x00000060 // Peripheral #1 assigned IVG13
#define P1_IVG14 0x00000070 // Peripheral #1 assigned IVG14
#define P1_IVG15 0x00000080 // Peripheral #1 assigned IVG15
#define P2_IVG7 0x00000000 // Peripheral #2 assigned IVG7
#define P2_IVG8 0x00000100 // Peripheral #2 assigned IVG8
#define P2_IVG9 0x00000200 // Peripheral #2 assigned IVG9
#define P2_IVG10 0x00000300 // Peripheral #2 assigned IVG10
#define P2_IVG11 0x00000400 // Peripheral #2 assigned IVG11
#define P2_IVG12 0x00000500 // Peripheral #2 assigned IVG12
#define P2_IVG13 0x00000600 // Peripheral #2 assigned IVG13
#define P2_IVG14 0x00000700 // Peripheral #2 assigned IVG14
#define P2_IVG15 0x00000800 // Peripheral #2 assigned IVG15
#define P3_IVG7 0x00000000 // Peripheral #3 assigned IVG7
#define P3_IVG8 0x00001000 // Peripheral #3 assigned IVG8
#define P3_IVG9 0x00002000 // Peripheral #3 assigned IVG9
#define P3_IVG10 0x00003000 // Peripheral #3 assigned IVG10
#define P3_IVG11 0x00004000 // Peripheral #3 assigned IVG11
#define P3_IVG12 0x00005000 // Peripheral #3 assigned IVG12
#define P3_IVG13 0x00006000 // Peripheral #3 assigned IVG13
#define P3_IVG14 0x00007000 // Peripheral #3 assigned IVG14
#define P3_IVG15 0x00008000 // Peripheral #3 assigned IVG15
#define P4_IVG7 0x00000000 // Peripheral #4 assigned IVG7
#define P4_IVG8 0x00010000 // Peripheral #4 assigned IVG8
#define P4_IVG9 0x00020000 // Peripheral #4 assigned IVG9
#define P4_IVG10 0x00030000 // Peripheral #4 assigned IVG10
#define P4_IVG11 0x00040000 // Peripheral #4 assigned IVG11
#define P4_IVG12 0x00050000 // Peripheral #4 assigned IVG12
#define P4_IVG13 0x00060000 // Peripheral #4 assigned IVG13
#define P4_IVG14 0x00070000 // Peripheral #4 assigned IVG14
#define P4_IVG15 0x00080000 // Peripheral #4 assigned IVG15
#define P5_IVG7 0x00000000 // Peripheral #5 assigned IVG7
#define P5_IVG8 0x00100000 // Peripheral #5 assigned IVG8
#define P5_IVG9 0x00200000 // Peripheral #5 assigned IVG9
#define P5_IVG10 0x00300000 // Peripheral #5 assigned IVG10
#define P5_IVG11 0x00400000 // Peripheral #5 assigned IVG11
#define P5_IVG12 0x00500000 // Peripheral #5 assigned IVG12
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