📄 def21535.h
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#define TIMER1_WIDTH_LO 0xFFC0201C // Timer 1 Width Register (low word)
#define TIMER1_WIDTH_HI 0xFFC0201E // Timer 1 Width Register (high word)
#define TIMER2_STATUS 0xFFC02020 // Timer 2 Global Status and Sticky Register
#define TIMER2_CONFIG 0xFFC02022 // Timer 2 configuration register
#define TIMER2_COUNTER_LO 0xFFC02024 // Timer 2 Counter Register (low word)
#define TIMER2_COUNTER_HI 0xFFC02026 // Timer 2 Counter Register (high word)
#define TIMER2_PERIOD_LO 0xFFC02028 // Timer 2 Period Register (low word)
#define TIMER2_PERIOD_HI 0xFFC0202A // Timer 2 Period Register (high word)
#define TIMER2_WIDTH_LO 0xFFC0202C // Timer 2 Width Register (low word)
#define TIMER2_WIDTH_HI 0xFFC0202E // Timer 2 Width Register (high word)
// General Purpose IO (0xFFC0 2400-0xFFC0 27FF)
#define FIO_DIR 0xFFC02400 // Peripheral Flag Direction Register
#define FIO_FLAG_C 0xFFC02404 // Peripheral Interrupt Flag Register (clear)
#define FIO_FLAG_S 0xFFC02406 // Peripheral Interrupt Flag Register (set)
#define FIO_MASKA_C 0xFFC02408 // Flag Mask Interrupt A Register (clear)
#define FIO_MASKA_S 0xFFC0240A // Flag Mask Interrupt A Register (set)
#define FIO_MASKB_C 0xFFC0240C // Flag Mask Interrupt B Register (clear)
#define FIO_MASKB_S 0xFFC0240E // Flag Mask Interrupt B Register (set)
#define FIO_POLAR 0xFFC02410 // Flag Source Polarity Register
#define FIO_EDGE 0xFFC02414 // Flag Source Sensitivity Register
#define FIO_BOTH 0xFFC02418 // Flag Set on BOTH Edges Register
// SPORT0 Controller (0xFFC0 2800-0xFFC0 2BFF)
#define SPORT0_TX_CONFIG 0xFFC02800 // SPORT0 Transmit Configuration Register
#define SPORT0_RX_CONFIG 0xFFC02802 // SPORT0 Receive Configuration Register
#define SPORT0_TX 0xFFC02804 // SPORT0 TX transmit Register
#define SPORT0_RX 0xFFC02806 // SPORT0 RX Receive register
#define SPORT0_TSCLKDIV 0xFFC02808 // SPORT0 Transmit Serial Clock Divider
#define SPORT0_RSCLKDIV 0xFFC0280A // SPORT0 Receive Serial Clock Divider
#define SPORT0_TFSDIV 0xFFC0280C // SPORT0 Transmit Frame Sync Divider
#define SPORT0_RFSDIV 0xFFC0280E // SPORT0 Receive Frame Sync Divider
#define SPORT0_STAT 0xFFC02810 // SPORT0 Status Register
#define SPORT0_MTCS0 0xFFC02812 // SPORT0 Multi-Channel Transmit Select Register
#define SPORT0_MTCS1 0xFFC02814 // SPORT0 Multi-Channel Transmit Select Register
#define SPORT0_MTCS2 0xFFC02816 // SPORT0 Multi-Channel Transmit Select Register
#define SPORT0_MTCS3 0xFFC02818 // SPORT0 Multi-Channel Transmit Select Register
#define SPORT0_MTCS4 0xFFC0281A // SPORT0 Multi-Channel Transmit Select Register
#define SPORT0_MTCS5 0xFFC0281C // SPORT0 Multi-Channel Transmit Select Register
#define SPORT0_MTCS6 0xFFC0281E // SPORT0 Multi-Channel Transmit Select Register
#define SPORT0_MTCS7 0xFFC02820 // SPORT0 Multi-Channel Transmit Select Register
#define SPORT0_MRCS0 0xFFC02822 // SPORT0 Multi-Channel Receive Select Register
#define SPORT0_MRCS1 0xFFC02824 // SPORT0 Multi-Channel Receive Select Register
#define SPORT0_MRCS2 0xFFC02826 // SPORT0 Multi-Channel Receive Select Register
#define SPORT0_MRCS3 0xFFC02828 // SPORT0 Multi-Channel Receive Select Register
#define SPORT0_MRCS4 0xFFC0282A // SPORT0 Multi-Channel Receive Select Register
#define SPORT0_MRCS5 0xFFC0282C // SPORT0 Multi-Channel Receive Select Register
#define SPORT0_MRCS6 0xFFC0282E // SPORT0 Multi-Channel Receive Select Register
#define SPORT0_MRCS7 0xFFC02830 // SPORT0 Multi-Channel Receive Select Register
#define SPORT0_MCMC1 0xFFC02832 // SPORT0 Multi-Channel Configuration Register 1
#define SPORT0_MCMC2 0xFFC02834 // SPORT0 Multi-Channel Configuration Register 2
#define SPORT0_CURR_PTR_RX 0xFFC02A00 // SPORT0 -RCV DMA Current Pointer
#define SPORT0_CONFIG_DMA_RX 0xFFC02A02 // SPORT0 -RCV DMA Configuration
#define SPORT0_START_ADDR_HI_RX 0xFFC02A04 // SPORT0 -RCV DMA Start Page
#define SPORT0_START_ADDR_LO_RX 0xFFC02A06 // SPORT0 -RCV DMA Start Address
#define SPORT0_COUNT_RX 0xFFC02A08 // SPORT0 -RCV DMA Count
#define SPORT0_NEXT_DESCR_RX 0xFFC02A0A // SPORT0 -RCV DMA Next Descriptor Pointer
#define SPORT0_DESCR_RDY_RX 0xFFC02A0C // SPORT0 -RCV DMA Descriptor Ready
#define SPORT0_IRQSTAT_RX 0xFFC02A0E // SPORT0 -RCV DMA Interrupt Register
#define SPORT0_CURR_PTR_TX 0xFFC02B00 // SPORT0 -XMT DMA Current Pointer
#define SPORT0_CONFIG_DMA_TX 0xFFC02B02 // SPORT0 -XMT DMA Configuration
#define SPORT0_START_ADDR_HI_TX 0xFFC02B04 // SPORT0 -XMT DMA Start Page
#define SPORT0_START_ADDR_LO_TX 0xFFC02B06 // SPORT0 -XMT DMA Start Address
#define SPORT0_COUNT_TX 0xFFC02B08 // SPORT0 -XMT DMA Count
#define SPORT0_NEXT_DESCR_TX 0xFFC02B0A // SPORT0 -XMT DMA Next Descriptor Pointer
#define SPORT0_DESCR_RDY_TX 0xFFC02B0C // SPORT0 -XMT DMA Descriptor Ready
#define SPORT0_IRQSTAT_TX 0xFFC02B0E // SPORT0 -XMT DMA Interrupt Register
// SPORT1 Controller (0xFFC0 2C00-0xFFC0 2FFF)
#define SPORT1_TX_CONFIG 0xFFC02C00 // SPORT1 Transmit Configuration Register
#define SPORT1_RX_CONFIG 0xFFC02C02 // SPORT1 Receive Configuration Register
#define SPORT1_TX 0xFFC02C04 // SPORT1 TX transmit Register
#define SPORT1_RX 0xFFC02C06 // SPORT1 RX Receive register
#define SPORT1_TSCLKDIV 0xFFC02C08 // SPORT1 Transmit Serial Clock Divider
#define SPORT1_RSCLKDIV 0xFFC02C0A // SPORT1 Receive Serial Clock Divider
#define SPORT1_TFSDIV 0xFFC02C0C // SPORT1 Transmit Frame Sync Divider
#define SPORT1_RFSDIV 0xFFC02C0E // SPORT1 Receive Frame Sync Divider
#define SPORT1_STAT 0xFFC02C10 // SPORT1 Status Register
#define SPORT1_MTCS0 0xFFC02C12 // SPORT1 Multi-Channel Transmit Select Register
#define SPORT1_MTCS1 0xFFC02C14 // SPORT1 Multi-Channel Transmit Select Register
#define SPORT1_MTCS2 0xFFC02C16 // SPORT1 Multi-Channel Transmit Select Register
#define SPORT1_MTCS3 0xFFC02C18 // SPORT1 Multi-Channel Transmit Select Register
#define SPORT1_MTCS4 0xFFC02C1A // SPORT1 Multi-Channel Transmit Select Register
#define SPORT1_MTCS5 0xFFC02C1C // SPORT1 Multi-Channel Transmit Select Register
#define SPORT1_MTCS6 0xFFC02C1E // SPORT1 Multi-Channel Transmit Select Register
#define SPORT1_MTCS7 0xFFC02C20 // SPORT1 Multi-Channel Transmit Select Register
#define SPORT1_MRCS0 0xFFC02C22 // SPORT1 Multi-Channel Receive Select Register
#define SPORT1_MRCS1 0xFFC02C24 // SPORT1 Multi-Channel Receive Select Register
#define SPORT1_MRCS2 0xFFC02C26 // SPORT1 Multi-Channel Receive Select Register
#define SPORT1_MRCS3 0xFFC02C28 // SPORT1 Multi-Channel Receive Select Register
#define SPORT1_MRCS4 0xFFC02C2A // SPORT1 Multi-Channel Receive Select Register
#define SPORT1_MRCS5 0xFFC02C2C // SPORT1 Multi-Channel Receive Select Register
#define SPORT1_MRCS6 0xFFC02C2E // SPORT1 Multi-Channel Receive Select Register
#define SPORT1_MRCS7 0xFFC02C30 // SPORT1 Multi-Channel Receive Select Register
#define SPORT1_MCMC1 0xFFC02C32 // SPORT1 Multi-Channel Configuration Register 1
#define SPORT1_MCMC2 0xFFC02C34 // SPORT1 Multi-Channel Configuration Register 2
#define SPORT1_CURR_PTR_RX 0xFFC02E00 // SPORT1 -RCV DMA Current Pointer
#define SPORT1_CONFIG_DMA_RX 0xFFC02E02 // SPORT1 -RCV DMA Configuration
#define SPORT1_START_ADDR_HI_RX 0xFFC02E04 // SPORT1 -RCV DMA Start Page
#define SPORT1_START_ADDR_LO_RX 0xFFC02E06 // SPORT1 -RCV DMA Start Address
#define SPORT1_COUNT_RX 0xFFC02E08 // SPORT1 -RCV DMA Count
#define SPORT1_NEXT_DESCR_RX 0xFFC02E0A // SPORT1 -RCV DMA Next Descriptor Pointer
#define SPORT1_DESCR_RDY_RX 0xFFC02E0C // SPORT1 -RCV DMA Descriptor Ready
#define SPORT1_IRQSTAT_RX 0xFFC02E0E // SPORT1 -RCV DMA Interrupt Register
#define SPORT1_CURR_PTR_TX 0xFFC02F00 // SPORT1 -XMT DMA Current Pointer
#define SPORT1_CONFIG_DMA_TX 0xFFC02F02 // SPORT1 -XMT DMA Configuration
#define SPORT1_START_ADDR_HI_TX 0xFFC02F04 // SPORT1 -XMT DMA Start Page
#define SPORT1_START_ADDR_LO_TX 0xFFC02F06 // SPORT1 -XMT DMA Start Address
#define SPORT1_COUNT_TX 0xFFC02F08 // SPORT1 -XMT DMA Count
#define SPORT1_NEXT_DESCR_TX 0xFFC02F0A // SPORT1 -XMT DMA Next Descriptor Pointer
#define SPORT1_DESCR_RDY_TX 0xFFC02F0C // SPORT1 -XMT DMA Descriptor Ready
#define SPORT1_IRQSTAT_TX 0xFFC02F0E // SPORT1 -XMT DMA Interrupt Register
// SPI 0 Controller (0xFFC0 3000-0xFFC0 33FF)
#define SPI0_CTL 0xFFC03000 // SPI0 Control Register
#define SPI0_FLG 0xFFC03002 // SPI0 Flag register
#define SPI0_ST 0xFFC03004 // SPI0 Status register
#define SPI0_TDBR 0xFFC03006 // SPI0 Transmit Data Buffer Register
#define SPI0_RDBR 0xFFC03008 // SPI0 Receive Data Buffer Register
#define SPI0_BAUD 0xFFC0300A // SPI0 Baud rate Register
#define SPI0_SHADOW 0xFFC0300C
#define SPI0_CURR_PTR 0xFFC03200 // SPI0 -DMA Current Pointer register
#define SPI0_CONFIG 0xFFC03202 // SPI0 -DMA Configuration register
#define SPI0_START_ADDR_HI 0xFFC03204 // SPI0 -DMA Start Page register
#define SPI0_START_ADDR_LO 0xFFC03206 // SPI0 -DMA Start Address register
#define SPI0_COUNT 0xFFC03208 // SPI0 -DMA Count register
#define SPI0_NEXT_DESCR 0xFFC0320A // SPI0 -DMA Next Descriptor Pointer
#define SPI0_DESCR_RDY 0xFFC0320C // SPI0 -DMA Descriptor Ready
#define SPI0_DMA_INT 0xFFC0320E // SPI0 -DMA Interrupt register
// SPI 1 Controller (0xFFC0 3400-0xFFC0 37FF)
#define SPI1_CTL 0xFFC03400 // SPI1 Control Register
#define SPI1_FLG 0xFFC03402 // SPI1 Flag register
#define SPI1_ST 0xFFC03404 // SPI1 Status register
#define SPI1_TDBR 0xFFC03406 // SPI1 Transmit Data Buffer Register
#define SPI1_RDBR 0xFFC03408 // SPI1 Receive Data Buffer Register
#define SPI1_BAUD 0xFFC0340A // SPI1 Baud rate Register
#define SPI1_SHADOW 0xFFC0340C
#define SPI1_CURR_PTR 0xFFC03600 // SPI1 -DMA Current Pointer register
#define SPI1_CONFIG 0xFFC03602 // SPI1 -DMA Configuration register
#define SPI1_START_ADDR_HI 0xFFC03604 // SPI1 -DMA Start Page register
#define SPI1_START_ADDR_LO 0xFFC03606 // SPI1 -DMA Start Address register
#define SPI1_COUNT 0xFFC03608 // SPI1 -DMA Count register
#define SPI1_NEXT_DESCR 0xFFC0360A // SPI1 -DMA Next Descriptor Pointer
#define SPI1_DESCR_RDY 0xFFC0360C // SPI1 -DMA Descriptor Ready
#define SPI1_DMA_INT 0xFFC0360E // SPI1 -DMA Interrupt register
// Memory DMA Controller (0xFFC0 3800-0xFFC0 3BFF)
#define MDW_DCP 0xFFC03800 // Current Pointer - Write Channel
#define MDW_DCFG 0xFFC03802 // DMA Configuration - Write Channel
#define MDW_DSAH 0xFFC03804 // Start Address Hi - Write Channel
#define MDW_DSAL 0xFFC03806 // Start Address Lo - Write Channel
#define MDW_DCT 0xFFC03808 // DMA Count - Write Channel
#define MDW_DND 0xFFC0380A // Next Descriptor Pointer - Write Channel
#define MDW_DDR 0xFFC0380C // Descriptor Ready - Write Channel
#define MDW_DI 0xFFC0380E // DMA Interrupt - Write Channel
#define MDR_DCP 0xFFC03900 // Current Pointer - Read Channel
#define MDR_DCFG 0xFFC03902 // DMA Configuration - Read Channel
#define MDR_DSAH 0xFFC03904 // Start Address Hi - Read Channel
#define MDR_DSAL 0xFFC03906 // Start Address Lo - Read Channel
#define MDR_DCT 0xFFC03908 // DMA Count - Read Channel
#define MDR_DND 0xFFC0390A // Next Descriptor Pointer - Read Channel
#define MDR_DDR 0xFFC0390C // Descriptor Ready - Read Channel
#define MDR_DI 0xFFC0390E // DMA Interrupt - Read Channel
// Aysnchronous Memory Controller - External Bus Interface Unit (0xFFC0 3C00-0xFFC0 3FFF)
#define EBIU_AMGCTL 0xFFC03C00 // Asynchronous Memory Global Control Register
#define EBIU_AMBCTL0 0xFFC03C04 // Asynchronous Memory Bank Control Register 0
#define EBIU_AMBCTL1 0xFFC03C08 // Asynchronous Memory Bank Control Register 1
// PCI Bridge PAB Registers (0xFFC0 4000-0xFFC0 43FF)
#define PCI_CTL 0xFFC04000 // PCI Bridge Control
#define PCI_STAT 0xFFC04004 // PCI Bridge Status
#define PCI_ICTL 0xFFC04008 // PCI Bridge Interrupt Control
#define PCI_MBAP 0xFFC0400C // PCI Memory Space Base Address Pointer [31:27]
#define PCI_IBAP 0xFFC04010 // PCI IO Space Base Address Pointer
#define PCI_CBAP 0xFFC04014 // PCI Config Space Base Address Port
#define PCI_TMBAP 0xFFC04018 // PCI to 21535 Memory Base Address Pointer
#define PCI_TIBAP 0xFFC0401C // PCI to 21535 IO Base Address Pointer
// PCI Bridge External Access Bus Registers (0xEEFF FF00-0xEEFF FFFF)
#define PCI_DMBARM 0xEEFFFF00 // PCI Device Memory Bar Mask
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