def21535.h

blankfin 的 dma 驱动控制代码

/*
** Copyright (C) 2001 Analog Devices Inc., All Rights Rerserved.
*/
//**********************************************************************************
// def21535.h - SYSTEM & MM REGISTER BIT & ADDRESS DEFINITIONS FOR ADSP-21535
// Last Revised: 5/8/01 JN, ADI
//
// This include file contains a list of macro "defines" to enable the programmer
// to use symbolic names for the following ADSP-21535 facilities:
//  
//  - System Register bit definitions
//  - Core MMR Register map
//  - System MMR Register map
//  - *some* Core MMR Register bit definitions
//  - *some* System MMR Register bit definitions
//
// Here is an example use for setting a bit in a system register using bitset and a bit position:
// The example enables the cycle counter in SYSCFG.
//
//  r0 = SYSCFG;
//  bitset (r0, CCEN_BIT);
//  SYSCFG = r0;
//
// Here is an example use for clearing a bit in a system register using bitclr and a bit position:
// The example disables the cycle counter in SYSCFG.
//
//  r0 = SYSCFG;
//  bitclr (r0, CCEN_BIT);
//  SYSCFG = r0;
//
//
// Here is an example use for setting multiple bits in a system register using a mask:
// The example enables the cycle counter and supervisor single step in SYSCFG.
//
//  r0 = SYSCFG;
//  r1.l = (CCEN | SSSTEP) & 0xffff;
//  r1.h = (CCEN | SSSTEP) >> 16;
//  r0 = r0 | r1;
//  SYSCFG = r0;
//
// Here is an example use for clearing multiple bits in a system register using a mask:
// The example disables the cycle counter and supervisor single step in SYSCFG.
//
//  r0 = SYSCFG;
//  r0 =~ r0;
//  r1.l = (CCEN | SSSTEP) & 0xffff;
//  r1.h = (CCEN | SSSTEP) >> 16;
//  r0 = r0 | r1;
//  r0 =~ r0;
//  SYSCFG = r0;
//
//**********************************************************************************


#ifndef __DEF_21535_H_
#define __DEF_21535_H_

// include all Core registers and bit definitions
#include <defBlackfin.h>


//**********************************************************************************
// System MMR Register Map
//**********************************************************************************

// L2 MISR MMRs (0xFFC0 0000-0xFFC0 03FF)
#define MISR_CTL               0xFFC00000     // Control Register
#define MISR_RMISR0            0xFFC00004     // coreL2[31:0] read bus
#define MISR_RMISR1            0xFFC00008     // coreL2[63:32] read bus
#define MISR_RMISR2            0xFFC0000C     // sysL2[31:0] read bus
#define MISR_WMISR0            0xFFC00010     // coreL2[31:0] write bus
#define MISR_WMISR1            0xFFC00014     // coreL2[63:32] write bus
#define MISR_WMISR2            0xFFC00018     // sysL2[31:0] write bus

// Clock and System Control (0xFFC0 0400-0xFFC0 07FF)
#define PLLCTL                 0xFFC00400      // PLL Control register (32-bit)
#define PLLSTAT                0xFFC00404      // PLL Status register
#define LOCKCNT                0xFFC00406      // PLL Lock Counter register
#define IOCKR                  0xFFC00408      // Peripheral Clock Enable register (32-bit)
#define SWRST                  0xFFC00410      // Software Reset Register

#define SYSCR                  0xFFC00414      // System Configuration register (RCSR)

// JTAG/Debug Communication Channel (0xFFC0 0800-0xFFC0 0BFF)
#define CHIPID                 0xFFC00808      // Device ID Register
 
// System Interrupt Controller (0xFFC0 0C00-0xFFC0 0FFF)
#define SIC_RVECT              0xFFC00C00  // Reset Vector Register
#define SIC_IAR0               0xFFC00C04  // Interrupt Assignment Register 0
#define SIC_IAR1               0xFFC00C08  // Interrupt Assignment Register 1
#define SIC_IAR2               0xFFC00C0C  // Interrupt Assignment Register 2
#define SIC_IMASK              0xFFC00C10  // Interrupt Mask Register
#define SIC_ISR                0xFFC00C14  // Interrupt Status Register
#define SIC_IWR                0xFFC00C18  // Interrupt Wakeup Register

// Watchdog Timer (0xFFC0 1000-0xFFC0 13FF)
#define WDOGCTL                0xFFC01000  // Watchdog Control Register
#define WDOGCNT                0xFFC01004  // Watchdog Count Register
#define WDOGSTAT               0xFFC01008  // Watchdog Status Register

// Real Time Clock (0xFFC0 1400-0xFFC0 17FF)
#define RTCSTAT                0xFFC01400  // RTC Status Register
#define RTCICTL                0xFFC01404  // RTC Interrupt Control Register
#define RTCISTAT               0xFFC01408  // RTC Interrupt Status Register
#define RTCSWCNT               0xFFC0140C  // RTC Stopwatch Count Register
#define RTCALARM               0xFFC01410  // RTC Alarm Time Register
#define RTCFAST                0xFFC01414  // RTC Prescaler Control Register

// UART 0 Controller (0xFFC0 1800-0xFFC0 1BFF)
#define UART0_THR              0xFFC01800  // Transmit Holding register
#define UART0_RBR              0xFFC01800  // Receive Buffer register
#define UART0_DLL              0xFFC01800  // Divisor Latch (Low-Byte)
#define UART0_IER              0xFFC01802  // Interrupt Enable Register
#define UART0_DLH              0xFFC01802  // Divisor Latch (High-Byte)
#define UART0_IIR              0xFFC01804  // Interrupt Identification Register
#define UART0_LCR              0xFFC01806  // Line Control Register
#define UART0_MCR              0xFFC01808  // Module Control Register
#define UART0_LSR              0xFFC0180A  // Line Status Register
#define UART0_MSR              0xFFC0180C  // MSR Modem Status Register
#define UART0_SCR              0xFFC0180E  // SCR Scratch Register
#define UART0_IRCR             0xFFC01810  // IRCR IrDA Control Register
#define UART0_CURR_PTR_RX      0xFFC01A00  // UART -DMA RCV Current Pointer register
#define UART0_CONFIG_RX        0xFFC01A02  // UART -RCV DMA Configuration register
#define UART0_START_ADDR_HI_RX 0xFFC01A04  // UART -RCV DMA Start Page register
#define UART0_START_ADDR_LO_RX 0xFFC01A06  // UART -RCV DMA Start Address register
#define UART0_COUNT_RX         0xFFC01A08  // UART -RCV DMA Count register
#define UART0_NEXT_DESCR_RX    0xFFC01A0A  // UART -RCV DMA Next Descriptor Pointer register
#define UART0_DESCR_RDY_RX     0xFFC01A0C  // UART -RCV DMA Descriptor Ready
#define UART0_IRQSTAT_RX       0xFFC01A0E  // UART -RCV DMA Interrupt Register
#define UART0_CURR_PTR_TX      0xFFC01B00  // UART -XMT DMA Current Pointer register
#define UART0_CONFIG_TX        0xFFC01B02  // UART -XMT DMA Configuration register
#define UART0_START_ADDR_HI_TX 0xFFC01B04  // UART -XMT DMA Start Page register
#define UART0_START_ADDR_LO_TX 0xFFC01B06  // UART -XMT DMA Start Address register
#define UART0_COUNT_TX         0xFFC01B08  // UART -XMT DMA Count register
#define UART0_NEXT_DESCR_TX    0xFFC01B0A  // UART -XMT DMA Next Descriptor Pointer register
#define UART0_DESCR_RDY_TX     0xFFC01B0C  // UART -XMT DMA Descriptor Ready
#define UART0_IRQSTAT_TX       0xFFC01B0E  // UART -XMT DMA Interrupt register

// UART 1 Controller (0xFFC0 1C00-0xFFC0 1FFF)
#define UART1_THR              0xFFC01C00  // Transmit Holding register
#define UART1_RBR              0xFFC01C00  // Receive Buffer register
#define UART1_DLL              0xFFC01C00  // Divisor Latch (Low-Byte)
#define UART1_IER              0xFFC01C02  // Interrupt Enable Register
#define UART1_DLH              0xFFC01C02  // Divisor Latch (High-Byte)
#define UART1_IIR              0xFFC01C04  // Interrupt Identification Register
#define UART1_LCR              0xFFC01C06  // Line Control Register
#define UART1_MCR              0xFFC01C08  // Module Control Register
#define UART1_LSR              0xFFC01C0A  // Line Status Register
#define UART1_MSR              0xFFC01C0C  // MSR Modem Status Register
#define UART1_SCR              0xFFC01C0E  // SCR Scratch Register
#define UART1_CURR_PTR_RX      0xFFC01E00  // UART -DMA RCV Current Pointer register
#define UART1_CONFIG_RX        0xFFC01E02  // UART -RCV DMA Configuration register
#define UART1_START_ADDR_HI_RX 0xFFC01E04  // UART -RCV DMA Start Page register
#define UART1_START_ADDR_LO_RX 0xFFC01E06  // UART -RCV DMA Start Address register
#define UART1_COUNT_RX         0xFFC01E08  // UART -RCV DMA Count register
#define UART1_NEXT_DESCR_RX    0xFFC01E0A  // UART -RCV DMA Next Descriptor Pointer register
#define UART1_DESCR_RDY_RX     0xFFC01E0C  // UART -RCV DMA Descriptor Ready
#define UART1_IRQSTAT_RX       0xFFC01E0E  // UART -RCV DMA Interrupt Register
#define UART1_CURR_PTR_TX      0xFFC01F00  // UART -XMT DMA Current Pointer register
#define UART1_CONFIG_TX        0xFFC01F02  // UART -XMT DMA Configuration register
#define UART1_START_ADDR_HI_TX 0xFFC01F04  // UART -XMT DMA Start Page register
#define UART1_START_ADDR_LO_TX 0xFFC01F06  // UART -XMT DMA Start Address register
#define UART1_COUNT_TX         0xFFC01F08  // UART -XMT DMA Count register
#define UART1_NEXT_DESCR_TX    0xFFC01F0A  // UART -XMT DMA Next Descriptor Pointer register
#define UART1_DESCR_RDY_TX     0xFFC01F0C  // UART -XMT DMA Descriptor Ready
#define UART1_IRQSTAT_TX       0xFFC01F0E  // UART -XMT DMA Interrupt register

// TIMER 0, 1, 2 Registers (0xFFC0 2000-0xFFC0 23FF)
#define TIMER0_STATUS          0xFFC02000  // Timer 0 Global Status and Sticky Register
#define TIMER0_CONFIG          0xFFC02002  // Timer 0 configuration Register
#define TIMER0_COUNTER_LO      0xFFC02004  // Timer 0 Counter Register (low word)
#define TIMER0_COUNTER_HI      0xFFC02006  // Timer 0 Counter Register (high word)
#define TIMER0_PERIOD_LO       0xFFC02008  // Timer 0 Period Register (low word)
#define TIMER0_PERIOD_HI       0xFFC0200A  // Timer 0 Period Register (high word)
#define TIMER0_WIDTH_LO        0xFFC0200C  // Timer 0 Width Register (low word)
#define TIMER0_WIDTH_HI        0xFFC0200E  // Timer 0 Width Register (high word)
#define TIMER1_STATUS          0xFFC02010  // Timer 1 Global Status and Sticky Register
#define TIMER1_CONFIG          0xFFC02012  // Timer 1 configuration register
#define TIMER1_COUNTER_LO      0xFFC02014  // Timer 1 Counter Register (low word)
#define TIMER1_COUNTER_HI      0xFFC02016  // Timer 1 Counter Register (high word)
#define TIMER1_PERIOD_LO       0xFFC02018  // Timer 1 Period Register (low word)
#define TIMER1_PERIOD_HI       0xFFC0201A  // Timer 1 Period Register (high word)