📄 flash.lst
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222 1 }
223
224
225 /*******************************************************/
226 /*******************************************************/
227 void Write_flash_hd(void)
228 {
229 1 if(write_F == 1)
230 1 {
231 2 if(write_delay_time != 0)
232 2 write_delay_time--;
233 2
234 2 if(write_delay_time == 0)
235 2 write_F = 0;
236 2 }
237 1 }
238
239 /*******************************************************/
240 /* 此函数用于测试硬件线路所用，向特定的RAM和FLASH中写入*/
241 /* 特定的数据，然后读出，就可据此判别硬件线路是否正常 */
C51 COMPILER V7.06 FLASH 06/10/2005 13:26:30 PAGE 5
242 /*******************************************************/
243 /*
244 unsigned char Test_hardware(void)
245 {
246 unsigned char hard_status = 0;
247 unsigned char test_step = 0;
248 while(test_step<3)
249 {
250 switch(test_step)
251 {
252 case 0: //测试RAM硬件线路
253 test_ram_adr1 = 0x00;
254 test_ram_adr2 = 0x55;
255 test_ram_adr3 = 0xaa;
256
257 if((test_ram_adr1 == 0x00)&&(test_ram_adr2 == 0x55)
258 &&(test_ram_adr3 == 0xaa))
259
260 test_step++; //如果RAM硬件没问题，再测试FLASH硬件线路
261
262 else //RAM硬件有问题，
263 {
264 hard_status = 1;
265 test_step = 3;
266 }
267 break;
268 case 1: // 先测试FLASH的首64K的硬件线路
269 Page_switch(PAGE_0);
270 special_addr1 = 0xaa;
271 special_addr2 = 0x55;
272 special_addr1 = 0xa0;
273 test_flash_adr1 = 0x00;
274 Delay_10ms();
275 special_addr1 = 0xaa;
276 special_addr2 = 0x55;
277 special_addr1 = 0xa0;
278 test_flash_adr2 = 0x55;
279 Delay_10ms();
280 special_addr1 = 0xaa;
281 special_addr2 = 0x55;
282 special_addr1 = 0xa0;
283 test_flash_adr3 = 0xaa;
284 Delay_10ms();
285
286 if((test_flash_adr1 == 0x00)&&(test_flash_adr2 == 0x55)
287 &&(test_flash_adr3 == 0xaa)) //FLASH 硬件没问题
288 test_step++;
289 else
290 {
291 hard_status = 2;
292 test_step = 3;
293 }
294 break;
295 case 2:
296 Page_switch(PAGE_1); // 测试FLASH的次64K的硬件线路
297 special_addr1 = 0xaa;
298 special_addr2 = 0x55;
299 special_addr1 = 0xa0;
300 test_flash_adr1 = 0x00;
301 Delay_10ms();
302 special_addr1 = 0xaa;
303 special_addr2 = 0x55;
C51 COMPILER V7.06 FLASH 06/10/2005 13:26:30 PAGE 6
304 special_addr1 = 0xa0;
305 test_flash_adr2 = 0x55;
306 Delay_10ms();
307 special_addr1 = 0xaa;
308 special_addr2 = 0x55;
309 special_addr1 = 0xa0;
310 test_flash_adr3 = 0xaa;
311 Delay_10ms();
312
313 if((test_flash_adr1 == 0x00)&&(test_flash_adr2 == 0x55)
314 &&(test_flash_adr3 == 0xaa))
315 test_step++;
316 else
317 {
318 hard_status = 3;
319 test_step++;
320 }
321 Page_switch(PAGE_0); //切换回正常状态
322 break;
323 default:
324 test_step = 3;
325 break;
326 }
327 }
328 Page_switch(PAGE_0);
329 return(hard_status);
330 }*/
C51 COMPILER V7.06 FLASH 06/10/2005 13:26:30 PAGE 7
ASSEMBLY LISTING OF GENERATED OBJECT CODE
; FUNCTION _Write_sector (BEGIN)
; SOURCE LINE # 48
0000 8C00 R MOV s_adr,R4
0002 8D00 R MOV s_adr+01H,R5
;---- Variable 'dst_adr' assigned to Register 'R6/R7' ----
; SOURCE LINE # 49
; SOURCE LINE # 52
0004 900000 E MOV DPTR,#special_addr1
0007 74AA MOV A,#0AAH
0009 F0 MOVX @DPTR,A
; SOURCE LINE # 53
000A 900000 E MOV DPTR,#special_addr2
000D 7455 MOV A,#055H
000F F0 MOVX @DPTR,A
; SOURCE LINE # 54
0010 900000 E MOV DPTR,#special_addr1
0013 74A0 MOV A,#0A0H
0015 F0 MOVX @DPTR,A
; SOURCE LINE # 58
0016 E4 CLR A
0017 F500 R MOV i,A
0019 F500 R MOV i+01H,A
001B ?C0001:
; SOURCE LINE # 59
; SOURCE LINE # 60
001B E500 R MOV A,s_adr+01H
001D 2500 R ADD A,i+01H
001F F582 MOV DPL,A
0021 E500 R MOV A,s_adr
0023 3500 R ADDC A,i
0025 F583 MOV DPH,A
0027 E0 MOVX A,@DPTR
0028 FD MOV R5,A
0029 EF MOV A,R7
002A 2500 R ADD A,i+01H
002C F582 MOV DPL,A
002E EE MOV A,R6
002F 3500 R ADDC A,i
0031 F583 MOV DPH,A
0033 ED MOV A,R5
0034 F0 MOVX @DPTR,A
; SOURCE LINE # 61
0035 0500 R INC i+01H
0037 E500 R MOV A,i+01H
0039 7002 JNZ ?C0040
003B 0500 R INC i
003D ?C0040:
003D B400DB CJNE A,#00H,?C0001
0040 E500 R MOV A,i
0042 B401D6 CJNE A,#01H,?C0001
; SOURCE LINE # 64
0045 ?C0004:
0045 22 RET
; FUNCTION _Write_sector (END)
; FUNCTION Code_init (BEGIN)
; SOURCE LINE # 69
; SOURCE LINE # 70
; SOURCE LINE # 71
C51 COMPILER V7.06 FLASH 06/10/2005 13:26:30 PAGE 8
0000 900000 E MOV DPTR,#init_code_b
0003 E0 MOVX A,@DPTR
0004 900000 E MOV DPTR,#init_code
0007 F0 MOVX @DPTR,A
; SOURCE LINE # 72
0008 900000 E MOV DPTR,#init_code_b+01H
000B E0 MOVX A,@DPTR
000C 900000 E MOV DPTR,#init_code+01H
000F F0 MOVX @DPTR,A
; SOURCE LINE # 73
0010 900000 E MOV DPTR,#init_code_b+02H
0013 E0 MOVX A,@DPTR
0014 900000 E MOV DPTR,#init_code+02H
0017 F0 MOVX @DPTR,A
; SOURCE LINE # 74
0018 22 RET
; FUNCTION Code_init (END)
; FUNCTION Mes_init (BEGIN)
; SOURCE LINE # 77
; SOURCE LINE # 78
; SOURCE LINE # 80
0000 E4 CLR A
0001 FF MOV R7,A
0002 120000 E LCALL _Page_switch
; SOURCE LINE # 82
0005 120000 R LCALL Code_init
; SOURCE LINE # 83
0008 900000 E MOV DPTR,#init_code
000B E0 MOVX A,@DPTR
000C B4A50D CJNE A,#0A5H,?C0006
000F A3 INC DPTR
0010 E0 MOVX A,@DPTR
0011 B45A08 CJNE A,#05AH,?C0006
0014 A3 INC DPTR
0015 E0 MOVX A,@DPTR
0016 B4AA03 CJNE A,#0AAH,?C0006
; SOURCE LINE # 84
; SOURCE LINE # 85
0019 020000 R LJMP Copy_mem
; SOURCE LINE # 86
001C ?C0006:
; SOURCE LINE # 88
; SOURCE LINE # 90
001C 120000 E LCALL Mes_tcb_init
; SOURCE LINE # 91
001F 900000 E MOV DPTR,#init_code
0022 74A5 MOV A,#0A5H
0024 F0 MOVX @DPTR,A
; SOURCE LINE # 92
0025 A3 INC DPTR
0026 745A MOV A,#05AH
0028 F0 MOVX @DPTR,A
; SOURCE LINE # 93
0029 A3 INC DPTR
002A 74AA MOV A,#0AAH
002C F0 MOVX @DPTR,A
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