sio_16c554.h

串口芯片驱动程序 驱动芯片为16C554。

//========================================================//
// Code Infomation:                                       //
//   This module defines the sio_16c554 IC constants  for //
//   programs of Board_DSP of MAIN_CONTROL                //
//   devices named 管理板CPU                              //
// Version: v1.01                                         //
// Programmer: Lejianxin                                  //
// Date:  Begined from 2005.02                            //
//        Last modified at                                //
// Copyright(c) 2002-2004  Shenzhen NARI Co.              //
//========================================================//

/* 程序修改记录(最新的放在最前面):                        *
 *  <修改日期>, <修改人员>: <修改功能概述>                *
 *========================================================*
  2.01 2005-02-28 10:25  Lejianxin written
 *========================================================*/

#ifndef _SIO_16C554_H_
#define _SIO_16C554_H_

#ifdef __cplusplus
extern "C"{
#endif

//==============================
// Address of 16C554 Registers

#define CN_SIO_RBR       (0x00)      // Receive Holding Register  (R/O) (LCR.7 = 0)
#define CN_SIO_THR       (0x00)      // Transmit Holding Register (W/O) (LCR.7 = 0)
#define CN_SIO_IER       (0x01)      // Interrupt Enable Register       (LCR.7 = 0)
#define CN_SIO_IIR       (0x02)      // Interupt identification Register (R/O)
#define CN_SIO_FCR       (0x02)      // FIFO Control register (W/O)
#define CN_SIO_LCR       (0x03)      // Line Control Register
#define CN_SIO_MCR       (0x04)      // Modem Control Register
#define CN_SIO_LSR       (0x05)      // Line Status register
#define CN_SIO_MSR       (0x06)      // Modem Status Register
#define CN_SIO_SCR       (0x07)      // Scratchpad Register

#define CN_SIO_DLL       (0x00)      // Divisor Latch Low    (with LCR.7 = 1)
#define CN_SIO_DLM       (0x01)      // Divisor Latch Middle (with LCR.7 = 1)


/* Line Control Register values */

#define CN_SIO_CHAR_LEN_5    0x00
#define CN_SIO_CHAR_LEN_6    0x01
#define CN_SIO_CHAR_LEN_7    0x02
#define CN_SIO_CHAR_LEN_8    0x03
#define CN_SIO_LCR_STB       0x04    /* Stop bit control */
#define CN_SIO_ONE_STOP      0x00    /* One stop bit! */
#define CN_SIO_LCR_PEN       0x08    /* Parity Enable */
#define CN_SIO_PARITY_NONE   0x00
#define CN_SIO_LCR_EPS       0x10    /* Even Parity Select */
#define CN_SIO_LCR_SP        0x20    /* Force Parity */
#define CN_SIO_LCR_SBRK      0x40    /* Start Break */
#define CN_SIO_LCR_DLAB      0x80    /* Divisor Latch Access Bit */
#define DLAB            CN_SIO_LCR_DLAB

/* Line Status Register */

#define LSR_DR          0x01    /* Data Ready */
#define LSR_OE          0x02    /* Overrun Error */
#define LSR_PE          0x04    /* Parity Error */
#define LSR_FE          0x08    /* Framing Error */
#define LSR_BI          0x10    /* Received Break Signal */
#define LSR_THRE        0x20    /* Transmit Holding Register Empty */
#define LSR_TEMT        0x40    /* THR and FIFO empty */
#define LSR_FERR        0x80    /* Parity, Framing error or break in FIFO */

#define RxCHAR_AVAIL    LSR_DR

/* Interrupt Identification Register */

#define IIR_MSTAT       0x00            /* Modem Status Register Int */
#define IIR_IP          0x01            /* Interrupt Pending */
#define IIR_THRE        0x02            /* THR Empty */
#define IIR_RDA         0x04            /* Rx Data Available */
#define IIR_RLS         0x06            /* Rx Line Status Int */
#define IIR_TIMEOUT     0x0C            /* Rx Data Timeout */
#define IIR_ID          0x0E            /* Interrupt source mask */

#define RxFIFO_INT      IIR_RDA
#define Rx_INT          IIR_RLS
#define TxFIFO_INT      IIR_THRE

/* Interrupt Enable Register */

#define IER_ERDAI       0x01            /* Enable Rx Data Available Int */
#define IER_ETHREI      0x02            /* Enable THR Empty Int */
#define IER_ELSI        0x04            /* Enable Line Status Int */
#define IER_EMSI        0x08            /* Enable Modem Status Int */
#define RxFIFO_BIT      IER_ERDAI
#define TxFIFO_BIT      IER_ETHREI
#define Rx_BIT          IER_ELSI

/* Modem Control Register */

#define MCR_DTR         0x01            /* state of DTR output */
#define MCR_RTS         0x02            /* state of RTS output */
#define MCR_OUT1        0x04            /* UNUSED in ST16554 */
#define MCR_INT         0x08            /* Int Mode */
#define MCR_LOOP        0x10            /* Enable Loopback mode */

#define DTR             MCR_DTR

/* Modem Status Register */

#define MSR_DCTS        0x01            /* change in CTS */
#define MSR_DDSR        0x02            /* change in DSR */
#define MSR_TERI        0x04            /* change in RI */
#define MSR_DDCD        0x08            /* change in DCD */
#define MSR_CTS         0x10            /* state of CTS input */
#define MSR_DSR         0x20            /* state of DSR input */
#define MSR_RI          0x40            /* state of RI input */
#define MSR_DCD         0x80            /* state of DCD input */

/* FIFO Control Register */

#define FCR_EN          0x01            /* FIFO Enable */
#define FCR_RXCLR       0x02            /* Rx FIFO Clear */
#define FCR_TXCLR       0x04            /* Tx FIFO Clear */
#define FCR_DMA         0x08            /* FIFO Mode Control */
#define FCR_RXTRIG_L    0x40            /* FIFO Trigger level Low */
#define FCR_RXTRIG_H    0x80            /* FIFO Trigger level High */

#define FIFO_ENABLE     FCR_EN
#define RxCLEAR         FCR_RXCLR
#define TxCLEAR         FCR_TXCLR


#ifdef __cplusplus
}
#endif

#endif /* _SIO_16C554_H_ */