can_sja1000.h

CAN 驱动程序

#ifndef _CAN_SJA1000_H_
#define _CAN_SJA1000_H_

#ifdef __cplusplus
extern "C" {
#endif


//============================================
// SJA1000 Registers for both BasicCAN & PeliCAN Mode
#define CN_CAN_CMR           ( 1)        // Command register
#define CN_CAN_SR            ( 2)        // Status  register
#define CN_CAN_IIR           ( 3)        // Interrupt identification register

//============================================
// SJA1000 Registers BasicCAN Mode
#define CN_BCAN_CR           ( 0)        // Control register ( including IER )
#define CN_BCAN_CMR          ( 1)        // Command register
#define CN_BCAN_SR           ( 2)        // Status  register
#define CN_BCAN_IIR          ( 3)        // Interrupt identification register
#define CN_BCAN_ACR          ( 4)        // Acceptance code register
#define CN_BCAN_AMR          ( 5)        // Acceptance mask register
#define CN_BCAN_BTR0         ( 6)        // Bus timing register 0
#define CN_BCAN_BTR1         ( 7)        // Bus timing register 1
#define CN_BCAN_OCR          ( 8)        // Output control register
#define CN_BCAN_TEST         ( 9)        // Test register
#define CN_BCAN_DSCR0        (10)        // Transmit buffer: Descriptor 0 (Identifier)
#define CN_BCAN_DSCR1        (11)        // Transmit buffer: Descriptor 1 (Controller)
#define CN_BCAN_FRAMENO      (12)        // Transmit buffer: FrameNo
#define CN_BCAN_TXD          (13)        // Transmit buffer: Data (13-19)
#define CN_BCAN_RXD          (20)        // Receive buffer: (20-29))
#define CN_BCAN_RX_LEN       (21)        // RX frame Length register
#define CN_BCAN_CDR          (31)        // Clock divider

//============================================
// SJA1000 Register PeliCAN mode
#define CN_PCAN_MODE         ( 0)        // Mode register
#define CN_PCAN_CMR          ( 1)        // Command register
#define CN_PCAN_SR           ( 2)        // Status register
#define CN_PCAN_IIR          ( 3)        // Interrupt identification register
#define CN_PCAN_IER          ( 4)        // Interrupt setting register
#define CN_PCAN_BTR0         ( 6)        // Bus timing register 0
#define CN_PCAN_BTR1         ( 7)        // Bus timing register 1
#define CN_PCAN_OCR          ( 8)        // Output control register
#define CN_PCAN_TEST         ( 9)        // Test register
#define CN_PCAN_ALC          (11)        // Arbitration lost capture register
#define CN_PCAN_ECC          (12)        // Error code capture register
#define CN_PCAN_EWL          (13)        // Error warning limit register
#define CN_PCAN_RXERR        (14)        // RX error counter register
#define CN_PCAN_TXERR        (15)        // TX error counter register
#define CN_PCAN_ACR0         (16)        // Acceptance code 0/RX(TX) frame information SFF(std) or EFF(Ext)
#define CN_PCAN_ACR1         (17)        // Acceptance code 1/RX(TX) identifier 1
#define CN_PCAN_ACR2         (18)        // Acceptance code 2/RX(TX) identifier 2
#define CN_PCAN_ACR3         (19)        // Acceptance code 3/RX(TX) data 1(SFF) or RX(TX) identifier 3(EFF)
#define CN_PCAN_AMR0         (20)        // Acceptance mask 0/RX(TX) data 2(SFF) or RX(TX) identifier 4(EFF)
#define CN_PCAN_AMR1         (21)        // Acceptance mask 1/RX(TX) data 3(SFF) or RX(TX) data 1
#define CN_PCAN_AMR2         (22)        // Acceptance mask 2/RX(TX) data 4(SFF) or RX(TX) data 2
#define CN_PCAN_AMR3         (23)        // Acceptance mask 3/RX(TX) data 5(SFF) or RX(TX) data 3
#define CN_PCAN_RXD          (16)        // Receive buffer [16-26(SFF) or 16-28(EFF)]
#define CN_PCAN_RX_LEN       (16)        // RX frame Length register(SFF)
#define CN_PCAN_DSCR0        (16)        // Transmit buffer: Descriptor 0 (Length)
#define CN_PCAN_DSCR1        (17)        // Transmit buffer: Descriptor 1 (Identifier)
#define CN_PCAN_DSCR2        (18)        // Transmit buffer: Descriptor 2 (controller)
#define CN_PCAN_FRAMENO      (19)        // Transmit buffer: FrameNo
#define CN_PCAN_TXD          (20)        // Transmit buffer: Data [20-26(SFF) or 22-28(EFF)]
#define CN_PCAN_RXMC         (29)        // RX message counter register
#define CN_PCAN_RBSA         (30)        // RX buffer start address register
#define CN_PCAN_CDR          (31)        // Clock divider register


#ifdef __cplusplus
}
#endif

#endif /* _CAN_SJA1000_H_ */