📄 init_ad50.asm.bak
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.include regs.h
.def init_AD50
NOP_REQ .set 0000h ; Pseudo reg0 val
REG1_RESET .set 0180h ; reset ad50c register1
REG1_VAL .set 0100h ; INP & INM for DAC, 15+1bit mode DAC
REG2_VAL .set 0200h ; unable telephonemode
REG3_VAL .set 0300h ; No delayed frame-sync
REG4_VAL .set 0430h ; Fs = MCLK/(128*N) = 8.192E6/(128*6)
; Gain: Input=0dB, Output=0db
SEC_REQ .set 0001h
.text
;==========================================================
; Initialize AD50 REG1, REG2, & REG4
; Default val for AD50 REG3
;==========================================================
init_AD50: portr DSP_CPLD_CNTL2, 60h ; select on-board AD50
nop
nop
andm 0FF00h, 60h
portw 60h, DSP_CPLD_CNTL2
nop
nop
stm 7FFFh,IFR ; clear BXINT1 flag
stm 0800h,IMR ; unmask BXINT1
stm SPCR2, McBSP1_SPSA ; enable McBSP1 Tx
orm 0001h, McBSP1_SPSD ; wait 2 SCLK cycle
nop
nop
nop
nop
LD #REG1_RESET,0,A
CALLD WAIT
NOP
NOP
LD #REG1_VAL,0,A ; ACCA=0x104
CALLD WAIT ; send to AD50
nop
nop
LD #REG2_VAL,0,A ; ACCA=0x210
CALLD WAIT ; send to AD50
nop
nop
LD #REG4_VAL,0,A ; ACCA=0x4F0
CALLD WAIT ; send to AD50
nop
nop
LD #REG3_VAL,A
CALLD WAIT
NOP
NOP
STM SPCR2, McBSP1_SPSA ; disable McBSP1 Tx
ANDM 0FFFEh, McBSP1_SPSD ; wait 2 SCLK cycle
nop
nop
RETD
nop
nop
WAIT: STM SEC_REQ, McBSP1_DXR1 ; McBSP1_DXR1=1
nop
STM 7FFFh,IFR ; clear BXINT1 flag
nop
idle 1 ; wait for BXINT1
STLM A,McBSP1_DXR1 ; ACCA=>McBSP1_DXR1
nop
STM 7FFFh,IFR ; clearBXINT1 flag
nop
idle 1 ; wait for BXINT1
RETD ; return
nop
nop
NOP
NOP
NOP
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