📄 blinky.asm
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CCU6_TCTR2L_T12SSC SET 0
CCU6_TCTR2L_T13SSC SET 0
CCU6_TCTR2L_T13TEC SET 0
CCU6_TCTR2L_T13TED SET 1
; RMAP=0 PAGE=0 - CCU6 Timer Control 4 Register High
CCU6_TCTR4H_T13RES SET 0
CCU6_TCTR4H_T13RR SET 0
CCU6_TCTR4H_T13RS SET 0
CCU6_TCTR4H_T13STD SET 0
CCU6_TCTR4H_T13STR SET 0
; RMAP=0 PAGE=0 - CCU6 Timer Control 4 Register Low
CCU6_TCTR4L_DTRES SET 0
CCU6_TCTR4L_T12RES SET 0
CCU6_TCTR4L_T12RR SET 0
CCU6_TCTR4L_T12RS SET 0
CCU6_TCTR4L_T12STD SET 0
CCU6_TCTR4L_T12STR SET 0
; RMAP=0 PAGE=2 - CCU6 Trap Control Register High
CCU6_TRPCTRH_TRPEN SET 0
CCU6_TRPCTRH_TRPEN13 SET 0
CCU6_TRPCTRH_TRPPEN SET 0
; RMAP=0 PAGE=2 - CCU6 Trap Control Register Low
CCU6_TRPCTRL_TRPM0 SET 0
CCU6_TRPCTRL_TRPM1 SET 0
CCU6_TRPCTRL_TRPM2 SET 0
; RMAP=0 PAGE=1 - SCU Clock Control Register
CMCON_CLKREL SET 0
; RMAP=x - CPU Data Pointer Register High
DPH_DPH0 SET 0
DPH_DPH1 SET 0
DPH_DPH2 SET 0
DPH_DPH3 SET 0
DPH_DPH4 SET 0
DPH_DPH5 SET 0
DPH_DPH6 SET 0
DPH_DPH7 SET 0
; RMAP=x - CPU Data Pointer Register Low
DPL_DPL0 SET 0
DPL_DPL1 SET 0
DPL_DPL2 SET 0
DPL_DPL3 SET 0
DPL_DPL4 SET 0
DPL_DPL5 SET 0
DPL_DPL6 SET 0
DPL_DPL7 SET 0
; RMAP=x - CPU Extended Operation Register
EO_DPSEL0 SET 0
EO_TRAP_EN SET 0
; RMAP=0 PAGE=0 - SCU External Interrupt Control Register 0
EXICON0_EXINT0 SET 0
EXICON0_EXINT1 SET 0
EXICON0_EXINT2 SET 0
EXICON0_EXINT3 SET 0
; RMAP=0 PAGE=0 - SCU External Interrupt Control Register 1
EXICON1_EXINT4 SET 0
EXICON1_EXINT5 SET 0
EXICON1_EXINT6 SET 0
; RMAP=0 PAGE=1 - SCU Flash Error Address Register High
FEAH_ECCERRADDR[15:8] SET 0
; RMAP=0 PAGE=1 - SCU Flash Error Address Register Low
FEAL_ECCERRADDR[7:0] SET 0
; RMAP=1 - OCDS Hardware Breakpoints Data Register
HWBPDR_HWBPXX SET 0
; RMAP=1 - OCDS Hardware Breakpoints Select Register
HWBPSR_BPSEL SET 0
HWBPSR_BPSEL_P SET 0
; RMAP=0 PAGE=1 - SCU Identity Register
ID_PRODID SET 0
ID_VERID SET 0
; RMAP=x - CPU Interrupt Enable 0 Register
IEN0_EA SET 1
IEN0_ES SET 0
IEN0_ET0 SET 1
IEN0_ET1 SET 0
IEN0_ET2 SET 0
IEN0_EX0 SET 0
IEN0_EX1 SET 0
; RMAP=x - CPU Module Interrupt Enable 1 Register
IEN1_EADC SET 0
IEN1_ECCIP0 SET 0
IEN1_ECCIP1 SET 0
IEN1_ECCIP2 SET 0
IEN1_ECCIP3 SET 0
IEN1_ESSC SET 0
IEN1_EX2 SET 0
IEN1_EXM SET 0
; RMAP=x - CPU Interrupt Priority 1 Register
IP1_PADC SET 0
IP1_PCCIP0 SET 0
IP1_PCCIP1 SET 0
IP1_PCCIP2 SET 0
IP1_PCCIP3 SET 0
IP1_PSSC SET 0
IP1_PX2 SET 0
IP1_PXM SET 0
; RMAP=x - CPU Interrupt Priority 1 High Register
IPH1_PADCH SET 0
IPH1_PCCIP0H SET 0
IPH1_PCCIP1H SET 0
IPH1_PCCIP2H SET 0
IPH1_PCCIP3H SET 0
IPH1_PSSCH SET 0
IPH1_PX2H SET 0
IPH1_PXMH SET 0
; RMAP=x - CPU Interrupt Priority High Register
IPH_PSH SET 0
IPH_PT0H SET 0
IPH_PT1H SET 0
IPH_PT2H SET 0
IPH_PX0H SET 0
IPH_PX1H SET 0
; RMAP=x - CPU Interrupt Priority Register
IP_PS SET 0
IP_PT0 SET 0
IP_PT1 SET 0
IP_PT2 SET 0
IP_PX0 SET 0
IP_PX1 SET 0
; RMAP=0 PAGE=0 - SCU Interrupt Request Register 0
IRCON0_EXINT0 SET 0
IRCON0_EXINT1 SET 0
IRCON0_EXINT2 SET 0
IRCON0_EXINT3 SET 0
IRCON0_EXINT4 SET 0
IRCON0_EXINT5 SET 0
IRCON0_EXINT6 SET 0
; RMAP=0 PAGE=0 - SCU Interrupt Request Register 1
IRCON1_ADCSRC0 SET 0
IRCON1_ADCSRC1 SET 0
IRCON1_EIR SET 0
IRCON1_RIR SET 0
IRCON1_TIR SET 0
; RMAP=1 - OCDS BreakPoints Control Register
MMBPCR_HWB0C SET 0
MMBPCR_HWB1C SET 0
MMBPCR_HWB2C SET 0
MMBPCR_HWB3C SET 0
MMBPCR_SWBC SET 0
; RMAP=1 - OCDS Monitor Mode Control 2 Register
MMCR2_EXBC SET 0
MMCR2_EXBC_P SET 0
MMCR2_JENA SET 0
MMCR2_MBCON SET 0
MMCR2_MBCON_P SET 0
MMCR2_MMEP SET 0
MMCR2_MMEP_P SET 0
MMCR2_MMODE SET 0
; RMAP=1 - OCDS Monitor Mode Control Register
MMCR_MEXIT SET 0
MMCR_MEXIT_P SET 0
MMCR_MRAMS SET 0
MMCR_MRAMS_P SET 0
MMCR_MSTEP SET 0
MMCR_MSTEP_P SET 0
MMCR_RRF SET 0
MMCR_TRF SET 0
; RMAP=1 - OCDS Monitor Mode Data Transfer Register Receive
MMDR_MMRR SET 0
; RMAP=1 - OCDS Monitor Mode Interrupt Control Register
MMICR_DRETR SET 0
MMICR_DVECT SET 0
MMICR_MMUIE SET 0
MMICR_MMUIE_P SET 0
MMICR_RRIE SET 0
MMICR_RRIE_P SET 0
; RMAP=1 - OCDS Monitor Mode Status Register
MMSR_EXBF SET 0
MMSR_HWB0F SET 0
MMSR_HWB1F SET 0
MMSR_HWB2F SET 0
MMSR_HWB3F SET 0
MMSR_MBCAM SET 0
MMSR_MBCIN SET 0
MMSR_SWBF SET 0
; RMAP=0 PAGE=0 - SCU Peripheral Input Select Register
MODPISEL_EXINT0IS SET 0
MODPISEL_JTAGTCKS SET 0
MODPISEL_JTAGTDIS SET 0
MODPISEL_URRIS SET 0
; RMAP=0 PAGE=0 - SCU NMI Control Register
NMICON_NMIECC SET 0
NMICON_NMIFLASHTIMER SET 0
NMICON_NMIOCDS SET 0
NMICON_NMIPLL SET 0
NMICON_NMIVDD SET 0
NMICON_NMIVDDP SET 0
NMICON_NMIWDT SET 0
; RMAP=0 PAGE=0 - SCU NMI Status Register
NMISR_FNMIECC SET 0
NMISR_FNMIFLASHTIMER SET 0
NMISR_FNMIOCDS SET 0
NMISR_FNMIPLL SET 0
NMISR_FNMIVDD SET 0
NMISR_FNMIVDDP SET 0
NMISR_FNMIWDT SET 0
; RMAP=0 PAGE=1 - SCU OSC Control Register
OSC_CON_ORDRES SET 0
OSC_CON_OSCPD SET 0
OSC_CON_OSCR SET 0
OSC_CON_OSCSS SET 1
OSC_CON_XPD SET 1
; RMAP=0 PAGE=2 - PORT P0 Alternate Select 0 Register
P0_ALTSEL0_P0 SET 0
P0_ALTSEL0_P1 SET 0
P0_ALTSEL0_P2 SET 0
P0_ALTSEL0_P3 SET 0
P0_ALTSEL0_P4 SET 0
P0_ALTSEL0_P5 SET 0
; RMAP=0 PAGE=2 - PORT P0 Alternate Select 1 Register
P0_ALTSEL1_P0 SET 0
P0_ALTSEL1_P1 SET 0
P0_ALTSEL1_P2 SET 0
P0_ALTSEL1_P3 SET 0
P0_ALTSEL1_P4 SET 0
P0_ALTSEL1_P5 SET 0
; RMAP=0 PAGE=0 - PORT P0 Data Register
P0_DATA_P0 SET 0
P0_DATA_P1 SET 0
P0_DATA_P2 SET 0
P0_DATA_P3 SET 0
P0_DATA_P4 SET 0
P0_DATA_P5 SET 0
; RMAP=0 PAGE=0 - PORT P0 Direction Register
P0_DIR_P0 SET 0
P0_DIR_P1 SET 0
P0_DIR_P2 SET 0
P0_DIR_P3 SET 0
P0_DIR_P4 SET 0
P0_DIR_P5 SET 0
; RMAP=0 PAGE=3 - PORT P0 Open Drain Control Register
P0_OD_P0 SET 0
P0_OD_P1 SET 0
P0_OD_P2 SET 0
P0_OD_P3 SET 0
P0_OD_P4 SET 0
P0_OD_P5 SET 0
; RMAP=0 PAGE=1 - PORT P0 Pull-Up/Pull-Down Enable Register
P0_PUDEN_P0 SET 0
P0_PUDEN_P1 SET 0
P0_PUDEN_P2 SET 1
P0_PUDEN_P3 SET 0
P0_PUDEN_P4 SET 0
P0_PUDEN_P5 SET 0
; RMAP=0 PAGE=1 - PORT P0 Pull-Up/Pull-Down Select Register
P0_PUDSEL_P0 SET 1
P0_PUDSEL_P1 SET 1
P0_PUDSEL_P2 SET 1
P0_PUDSEL_P3 SET 1
P0_PUDSEL_P4 SET 1
P0_PUDSEL_P5 SET 1
; RMAP=0 PAGE=2 - PORT P1 Alternate Select 0 Register
P1_ALTSEL0_P0 SET 0
P1_ALTSEL0_P1 SET 0
P1_ALTSEL0_P5 SET 0
P1_ALTSEL0_P6 SET 0
P1_ALTSEL0_P7 SET 0
; RMAP=0 PAGE=2 - PORT P1 Alternate Select 1 Register
P1_ALTSEL1_P0 SET 0
P1_ALTSEL1_P1 SET 1
P1_ALTSEL1_P5 SET 0
P1_ALTSEL1_P6 SET 0
P1_ALTSEL1_P7 SET 0
; RMAP=0 PAGE=0 - PORT P1 Data Register
P1_DATA_P0 SET 0
P1_DATA_P1 SET 0
P1_DATA_P5 SET 0
P1_DATA_P6 SET 0
P1_DATA_P7 SET 0
; RMAP=0 PAGE=0 - PORT P1 Direction Register
P1_DIR_P0 SET 0
P1_DIR_P1 SET 1
P1_DIR_P5 SET 0
P1_DIR_P6 SET 0
P1_DIR_P7 SET 0
; RMAP=0 PAGE=3 - PORT P1 Open Drain Control Register
P1_OD_P0 SET 0
P1_OD_P1 SET 0
P1_OD_P5 SET 0
P1_OD_P6 SET 0
P1_OD_P7 SET 0
; RMAP=0 PAGE=1 - PORT P1 Pull-Up/Pull-Down Enable Register
P1_PUDEN_P0 SET 1
P1_PUDEN_P1 SET 1
P1_PUDEN_P5 SET 1
P1_PUDEN_P6 SET 1
P1_PUDEN_P7 SET 1
; RMAP=0 PAGE=1 - PORT P1 Pull-Up/Pull-Down Select Register
P1_PUDSEL_P0 SET 1
P1_PUDSEL_P1 SET 1
P1_PUDSEL_P5 SET 1
P1_PUDSEL_P6 SET 1
P1_PUDSEL_P7 SET 1
; RMAP=0 PAGE=0 - PORT P2 Data Register
P2_DATA_P0 SET 0
P2_DATA_P1 SET 0
P2_DATA_P2 SET 0
P2_DATA_P3 SET 0
P2_DATA_P4 SET 0
P2_DATA_P5 SET 0
P2_DATA_P6 SET 0
P2_DATA_P7 SET 0
; RMAP=0 PAGE=1 - PORT P2 Pull-Up/Pull-Down Enable Register
P2_PUDEN_P0 SET 0
P2_PUDEN_P1 SET 0
P2_PUDEN_P2 SET 0
P2_PUDEN_P3 SET 0
P2_PUDEN_P4 SET 0
P2_PUDEN_P5 SET 0
P2_PUDEN_P6 SET 0
P2_PUDEN_P7 SET 0
; RMAP=0 PAGE=1 - PORT P2 Pull-Up/Pull-Down Select Register
P2_PUDSEL_P0 SET 1
P2_PUDSEL_P1 SET 1
P2_PUDSEL_P2 SET 1
P2_PUDSEL_P3 SET 1
P2_PUDSEL_P4 SET 1
P2_PUDSEL_P5 SET 1
P2_PUDSEL_P6 SET 1
P2_PUDSEL_P7 SET 1
; RMAP=0 PAGE=2 - PORT P3 Alternate Select 0 Register
P3_ALTSEL0_P0 SET 0
P3_ALTSEL0_P1 SET 0
P3_ALTSEL0_P2 SET 0
P3_ALTSEL0_P3 SET 0
P3_ALTSEL0_P4 SET 0
P3_ALTSEL0_P5 SET 0
P3_ALTSEL0_P6 SET 0
P3_ALTSEL0_P7 SET 0
; RMAP=0 PAGE=2 - PORT P3 Alternate Select 1 Register
P3_ALTSEL1_P0 SET 0
P3_ALTSEL1_P1 SET 0
P3_ALTSEL1_P2 SET 0
P3_ALTSEL1_P3 SET 0
P3_ALTSEL1_P4 SET 0
P3_ALTSEL1_P5 SET 0
P3_ALTSEL1_P6 SET 0
P3_ALTSEL1_P7 SET 0
; RMAP=0 PAGE=0 - PORT P3 Data Register
P3_DATA_P0 SET 0
P3_DATA_P1 SET 0
P3_DATA_P2 SET 0
P3_DATA_P3 SET 0
P3_DATA_P4 SET 0
P3_DATA_P5 SET 0
P3_DATA_P6 SET 0
P3_DATA_P7 SET 0
; RMAP=0 PAGE=0 - PORT P3 Direction Register
P3_DIR_P0 SET 1
P3_DIR_P1 SET 1
P3_DIR_P2 SET 1
P3_DIR_P3 SET 1
P3_DIR_P4 SET 1
P3_DIR_P5 SET 1
P3_DIR_P6 SET 1
P3_DIR_P7 SET 1
; RMAP=0 PAGE=3 - PORT P3 Open Drain Control Register
P3_OD_P0 SET 0
P3_OD_P1 SET 0
P3_OD_P2 SET 0
P3_OD_P3 SET 0
P3_OD_P4 SET 0
P3_OD_P5 SET 0
P3_OD_P6 SET 0
P3_OD_P7 SET 0
; RMAP=0 PAGE=1 - PORT P3 Pull-Up/Pull-Down Enable Register
P3_PUDEN_P0 SET 0
P3_PUDEN_P1 SET 0
P3_PUDEN_P2 SET 0
P3_PUDEN_P3 SET 0
P3_PUDEN_P4 SET 0
P3_PUDEN_P5 SET 0
P3_PUDEN_P6 SET 1
P3_PUDEN_P7 SET 0
; RMAP=0 PAGE=1 - PORT P3 Pull-Up/Pull-Down Select Register
P3_PUDSEL_P0 SET 1
P3_PUDSEL_P1 SET 1
P3_PUDSEL_P2 SET 1
P3_PUDSEL_P3 SET 1
P3_PUDSEL_P4 SET 1
P3_PUDSEL_P5 SET 1
P3_PUDSEL_P6 SET 0
P3_PUDSEL_P7 SET 1
; RMAP=0 PAGE=1 - SCU Password Register
PASSWD_MODE SET 0
PASSWD_PASS SET 0
PASSWD_PROTECT_S SET 0
; RMAP=x - CPU Power Control Register
PCON_GF0 SET 0
PCON_GF1 SET 0
PCON_IDLE SET 0
PCON_SMOD SET 0
; RMAP=0 PAGE=1 - SCU PLL Control Register
PLL_CON_LOCK SET 0
PLL_CON_NDIV SET 11
PLL_CON_OSCDISC SET 0
PLL_CON_RESLD SET 0
PLL_CON_VCOBYP SET 0
; RMAP=0 PAGE=1 - SCU Power Mode Control Register 0
PMCON0_PD SET 0
PMCON0_SD SET 0
PMCON0_WDTRST SET 0
PMCON0_WKRS SET 0
PMCON0_WKSEL SET 0
PMCON0_WS SET 0
; RMAP=0 PAGE=1 - SCU Power Mode Control Register 1
PMCON1_ADC_DIS SET 0
PMCON1_CCU_DIS SET 0
PMCON1_SSC_DIS SET 0
PMCON1_T2_DIS SET 0
; RMAP=0 - PORT Page Register
PORT_PAGE_OP SET 0
PORT_PAGE_PAGE SET 0
PORT_PAGE_STNR SET 0
; RMAP=x - CPU Program Status Word Register
PSW_AC SET 0
PSW_CY SET 0
PSW_F0 SET 0
PSW_F1 SET 0
PSW_OV SET 0
PSW_P SET 0
PSW_RS0 SET 0
PSW_RS1 SET 0
; RMAP=x - CPU Serial Data Buffer Register
SBUF_VAL SET 0
; RMAP=x - CPU Serial Channel Control Register
SCON_RB8 SET 0
SCON_REN SET 1
SCON_RI SET 0
SCON_SM0 SET 0
SCON_SM1 SET 1
SCON_SM2 SET 0
SCON_TB8 SET 0
SCON_TI SET 0
; RMAP=0 - SCU Page Register
SCU_PAGE_OP SET 0
SCU_PAGE_PAGE SET 0
SCU_PAGE_STNR SET 0
; RMAP=x - CPU Stack Pointer Register
SP_SP SET 0
; RMAP=0 - SSC Baudrate Timer Reload Register High
SSC_BRH_BR_VALUE[15:8] SET 0
; RMAP=0 - SSC Baudrate Timer Reload Register Low
SSC_BRL_BR_VALUE[7:0] SET 0
; RMAP=0 - SSC Module Control Register High, Operating Mode
SSC_CONH_O_BE SET 0
SSC_CONH_O_BSY SET 0
SSC_CONH_O_EN SET 0
SSC_CONH_O_MS SET 0
SSC_CONH_O_PE SET 0
SSC_CONH_O_RE SET 0
SSC_CONH_O_TE SET 0
; RMAP=0 - SSC Module Control Register High Programming Mode
SSC_CONH_P_AREN SET 0
SSC_CONH_P_BEN SET 0
SSC_CONH_P_EN SET 0
SSC_CONH_P_MS SET 0
SSC_CONH_P_PEN SET 0
SSC_CONH_P_REN SET 0
SSC_CONH_P_TEN SET 0
; RMAP=0 - SSC Module Control Register Low, Operating Mode
SSC_CONL_O_BC SET 0
; RMAP=0 - SSC Module Control Register Low Programming Mode
SSC_CONL_P_BM SET 1
SSC_CONL_P_HB SET 0
SSC_CONL_P_LB SET 0
SSC_CONL_P_PH SET 0
SSC_CONL_P_PO SET 0
; RMAP=0 - SSC Port Input Select Register
SSC_PISEL_CIS SET 0
SSC_PISEL_MIS SET 0
SSC_PISEL_SIS SET 0
; RMAP=0 - SSC Receiver Buffer Register Low
SSC_RBL_RB_VALUE SET 0
; RMAP=0 - SSC Transmitter Buffer Register Low
SSC_TBL_TB_VALUE SET 0
; RMAP=x - SCU System Control Register 0
SYSCON0_RMAP SET 0
; RMAP=0 - T2 Timer 2 Reload/Capture Register High
T2_RC2H_RC2[15:8] SET 0
; RMAP=0 - T2 Timer 2 Reload/Capture Register Low
T2_RC2L_RC2[7:0] SET 0
; RMAP=0 - T2 Timer 2 Control Register
T2_T2CON_CP_RL2 SET 0
T2_T2CON_EXEN2 SET 0
T2_T2CON_EXF2 SET 0
T2_T2CON_TF2 SET 0
T2_T2CON_TR2 SET 0
; RMAP=0 - T2 Timer 2 Register High
T2_T2H_THL2[15:8] SET 0
; RMAP=0 - T2 Timer 2 Register Low
T2_T2L_THL2[7:0] SET 0
; RMAP=0 - T2 Timer 2 Mode Register
T2_T2MOD_DCEN SET 0
T2_T2MOD_EDGESEL SET 0
T2_T2MOD_PREN SET 0
T2_T2MOD_T2PRE SET 0
; RMAP=x - CPU Timer Control Register
TCON_IE0 SET 0
TCON_IE1 SET 0
TCON_IT0 SET 0
TCON_IT1 SET 0
TCON_TF0 SET 0
TCON_TF1 SET 0
TCON_TR0 SET 1
TCON_TR1 SET 0
; RMAP=x - CPU Timer 0 Register High
TH0_VAL SET 0
; RMAP=x - CPU Timer 1 Register High
TH1_VAL SET 0
; RMAP=x - CPU Timer 0 Register Low
TL0_VAL SET 0
; RMAP=x - CPU Timer 1 Register Low
TL1_VAL SET 0
; RMAP=x - CPU Timer Mode Register
TMOD_GATE0 SET 0
TMOD_GATE1 SET 0
TMOD_T0M SET 2
TMOD_T1M SET 0
; RMAP=1 - WDT Watchdog Timer Control Register
WDTCON_WDTEN SET 0
WDTCON_WDTIN SET 0
WDTCON_WDTPR SET 0
WDTCON_WDTRS SET 0
WDTCON_WINBEN SET 0
; RMAP=1 - WDT Watchdog Timer Register High
WDTH_WDT[15:8] SET 0
; RMAP=1 - WDT Watchdog Timer Register Low
WDTL_WDT[7:0] SET 0
; RMAP=1 - WDT Watchdog Timer Reload Register
WDTREL_WDTREL SET 0
; RMAP=1 - WDT Watchdog Window-Boundary Count Register
WDTWINB_WDTWINB SET 0
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