📄 blinky.asm
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;****************************************************************************
; Filename keiltest.asm
; Project keiltest.DAV
;----------------------------------------------------------------------------
; Description This file contains the assembler formatted information
; about the actual project values. It will be used by your
; programming environment.
;
; PLEASE DO NOT MODIFY THIS FILE !
;
;----------------------------------------------------------------------------
; Date 10.02.2005 10:10:14
;
;****************************************************************************
; RMAP=0 PAGE=1 - ADC Channel 0 Control Register
ADC_CHCTR0_LCC SET 0
ADC_CHCTR0_RESRSEL SET 0
; RMAP=0 PAGE=1 - ADC Channel 1 Control Register
ADC_CHCTR1_LCC SET 0
ADC_CHCTR1_RESRSEL SET 0
; RMAP=0 PAGE=1 - ADC Channel 2 Control Register
ADC_CHCTR2_LCC SET 0
ADC_CHCTR2_RESRSEL SET 0
; RMAP=0 PAGE=1 - ADC Channel 3 Control Register
ADC_CHCTR3_LCC SET 0
ADC_CHCTR3_RESRSEL SET 0
; RMAP=0 PAGE=1 - ADC Channel 4 Control Register
ADC_CHCTR4_LCC SET 0
ADC_CHCTR4_RESRSEL SET 0
; RMAP=0 PAGE=1 - ADC Channel 5 Control Register
ADC_CHCTR5_LCC SET 0
ADC_CHCTR5_RESRSEL SET 0
; RMAP=0 PAGE=1 - ADC Channel 6 Control Register
ADC_CHCTR6_LCC SET 0
ADC_CHCTR6_RESRSEL SET 0
; RMAP=0 PAGE=1 - ADC Channel 7 Control Register
ADC_CHCTR7_LCC SET 0
ADC_CHCTR7_RESRSEL SET 0
; RMAP=0 PAGE=5 - ADC Channel Interrupt Clear Register
ADC_CHINCR_CHINC0 SET 0
ADC_CHINCR_CHINC1 SET 0
ADC_CHINCR_CHINC2 SET 0
ADC_CHINCR_CHINC3 SET 0
ADC_CHINCR_CHINC4 SET 0
ADC_CHINCR_CHINC5 SET 0
ADC_CHINCR_CHINC6 SET 0
ADC_CHINCR_CHINC7 SET 0
; RMAP=0 PAGE=5 - ADC Channel Interrupt Flag Register
ADC_CHINFR_CHINF0 SET 0
ADC_CHINFR_CHINF1 SET 0
ADC_CHINFR_CHINF2 SET 0
ADC_CHINFR_CHINF3 SET 0
ADC_CHINFR_CHINF4 SET 0
ADC_CHINFR_CHINF5 SET 0
ADC_CHINFR_CHINF6 SET 0
ADC_CHINFR_CHINF7 SET 0
; RMAP=0 PAGE=5 - ADC Channel Interrupt Node Pointer Register
ADC_CHINPR_CHINP0 SET 0
ADC_CHINPR_CHINP1 SET 0
ADC_CHINPR_CHINP2 SET 0
ADC_CHINPR_CHINP3 SET 0
ADC_CHINPR_CHINP4 SET 0
ADC_CHINPR_CHINP5 SET 0
ADC_CHINPR_CHINP6 SET 0
ADC_CHINPR_CHINP7 SET 0
; RMAP=0 PAGE=5 - ADC Channel Interrupt Set Register
ADC_CHINSR_CHINS0 SET 0
ADC_CHINSR_CHINS1 SET 0
ADC_CHINSR_CHINS2 SET 0
ADC_CHINSR_CHINS3 SET 0
ADC_CHINSR_CHINS4 SET 0
ADC_CHINSR_CHINS5 SET 0
ADC_CHINSR_CHINS6 SET 0
ADC_CHINSR_CHINS7 SET 0
; RMAP=0 PAGE=6 - ADC Source 1 Conversion Request Control Register
ADC_CRCR1_CH4 SET 0
ADC_CRCR1_CH5 SET 0
ADC_CRCR1_CH6 SET 0
ADC_CRCR1_CH7 SET 0
; RMAP=0 PAGE=6 - ADC Source 1 Conversion Request Mode Register
ADC_CRMR1_CLRPND SET 0
ADC_CRMR1_ENGT SET 0
ADC_CRMR1_ENSI SET 0
ADC_CRMR1_ENTR SET 0
ADC_CRMR1_LDEV SET 0
ADC_CRMR1_SCAN SET 0
; RMAP=0 PAGE=6 - ADC Source 1 Conversion Request Pending Register
ADC_CRPR1_CHP4 SET 0
ADC_CRPR1_CHP5 SET 0
ADC_CRPR1_CHP6 SET 0
ADC_CRPR1_CHP7 SET 0
; RMAP=0 PAGE=0 - ADC External Trigger Control Register
ADC_ETRCR_ETRSEL0 SET 0
ADC_ETRCR_ETRSEL1 SET 0
ADC_ETRCR_SYNEN0 SET 0
ADC_ETRCR_SYNEN1 SET 0
; RMAP=0 PAGE=5 - ADC Event Interrupt Clear Register
ADC_EVINCR_EVINC0 SET 0
ADC_EVINCR_EVINC1 SET 0
ADC_EVINCR_EVINC4 SET 0
ADC_EVINCR_EVINC5 SET 0
ADC_EVINCR_EVINC6 SET 0
ADC_EVINCR_EVINC7 SET 0
; RMAP=0 PAGE=5 - ADC Event Interrupt Flag Register
ADC_EVINFR_EVINF0 SET 0
ADC_EVINFR_EVINF1 SET 0
ADC_EVINFR_EVINF4 SET 0
ADC_EVINFR_EVINF5 SET 0
ADC_EVINFR_EVINF6 SET 0
ADC_EVINFR_EVINF7 SET 0
; RMAP=0 PAGE=5 - ADC Event Interrupt Node Pointer Register
ADC_EVINPR_EVINP0 SET 0
ADC_EVINPR_EVINP1 SET 0
ADC_EVINPR_EVINP4 SET 0
ADC_EVINPR_EVINP5 SET 0
ADC_EVINPR_EVINP6 SET 0
ADC_EVINPR_EVINP7 SET 0
; RMAP=0 PAGE=5 - ADC Event Interrupt Set Flag Register
ADC_EVINSR_EVINS0 SET 0
ADC_EVINSR_EVINS1 SET 0
ADC_EVINSR_EVINS4 SET 0
ADC_EVINSR_EVINS5 SET 0
ADC_EVINSR_EVINS6 SET 0
ADC_EVINSR_EVINS7 SET 0
; RMAP=0 PAGE=0 - ADC Global Control Register
ADC_GLOBCTR_ANON SET 0
ADC_GLOBCTR_CTC SET 3
ADC_GLOBCTR_DW SET 0
; RMAP=0 PAGE=0 - ADC Global Status Register
ADC_GLOBSTR_BUSY SET 0
ADC_GLOBSTR_CHNR SET 0
ADC_GLOBSTR_SAMPLE SET 0
; RMAP=0 PAGE=0 - ADC Input Class 0 Register
ADC_INPCR0_STC SET 0
; RMAP=0 PAGE=0 - ADC Limit Check Boundary Register
ADC_LCBR_BOUND0 SET 7
ADC_LCBR_BOUND1 SET 11
; RMAP=0 - ADC Page Register
ADC_PAGE_OP SET 0
ADC_PAGE_PAGE SET 0
ADC_PAGE_STNR SET 0
; RMAP=0 PAGE=0 - ADC Priority and Arbitration Register
ADC_PRAR_ARBM SET 0
ADC_PRAR_ASEN0 SET 0
ADC_PRAR_ASEN1 SET 0
ADC_PRAR_CSM0 SET 0
ADC_PRAR_CSM1 SET 0
ADC_PRAR_PRIO0 SET 0
ADC_PRAR_PRIO1 SET 0
; RMAP=0 PAGE=6 - ADC Source 0 Queue 0 Register
ADC_Q0R0_ENSI SET 0
ADC_Q0R0_EXTR SET 0
ADC_Q0R0_REQCHNR SET 0
ADC_Q0R0_RF SET 0
ADC_Q0R0_V SET 0
; RMAP=0 PAGE=6 - ADC Source 0 Queue Backup Register
ADC_QBUR0_ENSI SET 0
ADC_QBUR0_EXTR SET 0
ADC_QBUR0_REQCHNR SET 0
ADC_QBUR0_RF SET 0
ADC_QBUR0_V SET 0
; RMAP=0 PAGE=6 - ADC Source 0 Queue Input Register
ADC_QINR0_ENSI SET 0
ADC_QINR0_EXTR SET 0
ADC_QINR0_REQCHNR SET 0
ADC_QINR0_RF SET 0
; RMAP=0 PAGE=6 - ADC Source 0 Queue Mode Register
ADC_QMR0_CEV SET 0
ADC_QMR0_CLRV SET 0
ADC_QMR0_ENGT SET 0
ADC_QMR0_ENTR SET 0
ADC_QMR0_FLUSH SET 0
ADC_QMR0_TREV SET 0
ADC_QMR0_TRMD SET 0
; RMAP=0 PAGE=6 - ADC Source 0 Queue Status Register
ADC_QSR0_EMPTY SET 0
ADC_QSR0_EV SET 0
; RMAP=0 PAGE=4 - ADC Result 0 Control Register
ADC_RCR0_DRCTR SET 0
ADC_RCR0_FEN SET 0
ADC_RCR0_IEN SET 0
ADC_RCR0_VFCTR SET 0
ADC_RCR0_WFR SET 0
; RMAP=0 PAGE=4 - ADC Result 1 Control Register
ADC_RCR1_DRCTR SET 0
ADC_RCR1_FEN SET 0
ADC_RCR1_IEN SET 0
ADC_RCR1_VFCTR SET 0
ADC_RCR1_WFR SET 0
; RMAP=0 PAGE=4 - ADC Result 2 Control Register
ADC_RCR2_DRCTR SET 0
ADC_RCR2_FEN SET 0
ADC_RCR2_IEN SET 0
ADC_RCR2_VFCTR SET 0
ADC_RCR2_WFR SET 0
; RMAP=0 PAGE=4 - ADC Result 3 Control Register
ADC_RCR3_DRCTR SET 0
ADC_RCR3_FEN SET 0
ADC_RCR3_IEN SET 0
ADC_RCR3_VFCTR SET 0
ADC_RCR3_WFR SET 0
; RMAP=0 PAGE=2 - ADC Result 0 Register High
ADC_RESR0H_RESULT[9:2] SET 0
; RMAP=0 PAGE=2 - ADC Result 0 Register Low
ADC_RESR0L_CHNR SET 0
ADC_RESR0L_DRC SET 0
ADC_RESR0L_RESULT[1:0] SET 0
ADC_RESR0L_VF SET 0
; RMAP=0 PAGE=2 - ADC Result 1 Register High
ADC_RESR1H_RESULT[9:2] SET 0
; RMAP=0 PAGE=2 - ADC Result 1 Register Low
ADC_RESR1L_CHNR SET 0
ADC_RESR1L_DRC SET 0
ADC_RESR1L_RESULT[1:0] SET 0
ADC_RESR1L_VF SET 0
; RMAP=0 PAGE=2 - ADC Result 2 Register High
ADC_RESR2H_RESULT[9:2] SET 0
; RMAP=0 PAGE=2 - ADC Result 2 Register Low
ADC_RESR2L_CHNR SET 0
ADC_RESR2L_DRC SET 0
ADC_RESR2L_RESULT[1:0] SET 0
ADC_RESR2L_VF SET 0
; RMAP=0 PAGE=2 - ADC Result 3 Register High
ADC_RESR3H_RESULT[9:2] SET 0
; RMAP=0 PAGE=2 - ADC Result 3 Register Low
ADC_RESR3L_CHNR SET 0
ADC_RESR3L_DRC SET 0
ADC_RESR3L_RESULT[1:0] SET 0
ADC_RESR3L_VF SET 0
; RMAP=0 PAGE=3 - ADC Result 0 View A Register High
ADC_RESRA0H_RESULT[10:3] SET 0
; RMAP=0 PAGE=3 - ADC Result 0 View A Register Low
ADC_RESRA0L_CHNR SET 0
ADC_RESRA0L_DRC SET 0
ADC_RESRA0L_RESULT[2:0] SET 0
ADC_RESRA0L_VF SET 0
; RMAP=0 PAGE=3 - ADC Result 1 View A Register High
ADC_RESRA1H_RESULT[10:3] SET 0
; RMAP=0 PAGE=3 - ADC Result 1 View A Register Low
ADC_RESRA1L_CHNR SET 0
ADC_RESRA1L_DRC SET 0
ADC_RESRA1L_RESULT[2:0] SET 0
ADC_RESRA1L_VF SET 0
; RMAP=0 PAGE=3 - ADC Result 2 View A Register High
ADC_RESRA2H_RESULT[10:3] SET 0
; RMAP=0 PAGE=3 - ADC Result 2 View A Register Low
ADC_RESRA2L_CHNR SET 0
ADC_RESRA2L_DRC SET 0
ADC_RESRA2L_RESULT[2:0] SET 0
ADC_RESRA2L_VF SET 0
; RMAP=0 PAGE=3 - ADC Result 3 View A Register High
ADC_RESRA3H_RESULT[10:3] SET 0
; RMAP=0 PAGE=3 - ADC Result 3 View A Register Low
ADC_RESRA3L_CHNR SET 0
ADC_RESRA3L_DRC SET 0
ADC_RESRA3L_RESULT[2:0] SET 0
ADC_RESRA3L_VF SET 0
; RMAP=0 PAGE=4 - ADC Valid Flag Clear Register
ADC_VFCR_VFC0 SET 0
ADC_VFCR_VFC1 SET 0
ADC_VFCR_VFC2 SET 0
ADC_VFCR_VFC3 SET 0
; RMAP=x - CPU Accumulator Register
A_ACC0 SET 0
A_ACC1 SET 0
A_ACC2 SET 0
A_ACC3 SET 0
A_ACC4 SET 0
A_ACC5 SET 0
A_ACC6 SET 0
A_ACC7 SET 0
; RMAP=0 PAGE=0 - SCU Baud Rate Control Register
BCON_BGSEL SET 0
BCON_BREN SET 0
BCON_BRPRE SET 0
BCON_R SET 1
BCON_T2EXIS SET 0
; RMAP=0 PAGE=0 - SCU Baud Rate Timer/Reload Register
BG_BR_VALUE SET 173
; RMAP=x - CPU B Register
B_B0 SET 0
B_B1 SET 0
B_B2 SET 0
B_B3 SET 0
B_B4 SET 0
B_B5 SET 0
B_B6 SET 0
B_B7 SET 0
; RMAP=0 PAGE=1 - CCU6 Capture/Compare Register for Channel CC60 High
CCU6_CC60RH_CC60VH SET 0
; RMAP=0 PAGE=1 - CCU6 Capture/Compare Register for Channel CC60 Low
CCU6_CC60RL_CC60VL SET 0
; RMAP=0 PAGE=0 - CCU6 Capture/Compare Shadow Register for Channel CC60 High
CCU6_CC60SRH_CC60SH SET 0
; RMAP=0 PAGE=0 - CCU6 Capture/Compare Shadow Register for Channel CC60 Low
CCU6_CC60SRL_CC60SL SET 0
; RMAP=0 PAGE=1 - CCU6 Capture/Compare Register for Channel CC61 High
CCU6_CC61RH_CC61VH SET 0
; RMAP=0 PAGE=1 - CCU6 Capture/Compare Register for Channel CC61 Low
CCU6_CC61RL_CC61VL SET 0
; RMAP=0 PAGE=0 - CCU6 Capture/Compare Shadow Register for Channel CC61 High
CCU6_CC61SRH_CC61SH SET 0
; RMAP=0 PAGE=0 - CCU6 Capture/Compare Shadow Register for Channel CC61 Low
CCU6_CC61SRL_CC61SL SET 0
; RMAP=0 PAGE=1 - CCU6 Capture/Compare Register for Channel CC62 High
CCU6_CC62RH_CC62VH SET 0
; RMAP=0 PAGE=1 - CCU6 Capture/Compare Register for Channel CC62 Low
CCU6_CC62RL_CC62VL SET 0
; RMAP=0 PAGE=0 - CCU6 Capture/Compare Shadow Register for Channel CC62 High
CCU6_CC62SRH_CC62SH SET 0
; RMAP=0 PAGE=0 - CCU6 Capture/Compare Shadow Register for Channel CC62 Low
CCU6_CC62SRL_CC62SL SET 0
; RMAP=0 PAGE=1 - CCU6 Capture/Compare Register for Channel CC63 High
CCU6_CC63RH_CC63VH SET 0
; RMAP=0 PAGE=1 - CCU6 Capture/Compare Register for Channel CC63 Low
CCU6_CC63RL_CC63VL SET 0
; RMAP=0 PAGE=0 - CCU6 Capture/Compare Shadow Register for Channel CC63 High
CCU6_CC63SRH_CC63SH SET 0
; RMAP=0 PAGE=0 - CCU6 Capture/Compare Shadow Register for Channel CC63 Low
CCU6_CC63SRL_CC63SL SET 0
; RMAP=0 PAGE=0 - CCU6 Compare State Modification Register High
CCU6_CMPMODIFH_MCC60R SET 0
CCU6_CMPMODIFH_MCC61R SET 0
CCU6_CMPMODIFH_MCC62R SET 0
CCU6_CMPMODIFH_MCC63R SET 0
; RMAP=0 PAGE=0 - CCU6 Compare State Modification Register Low
CCU6_CMPMODIFL_MCC60S SET 0
CCU6_CMPMODIFL_MCC61S SET 0
CCU6_CMPMODIFL_MCC62S SET 0
CCU6_CMPMODIFL_MCC63S SET 0
; RMAP=0 PAGE=3 - CCU6 Compare State Register High
CCU6_CMPSTATH_CC60PS SET 0
CCU6_CMPSTATH_CC61PS SET 0
CCU6_CMPSTATH_CC62PS SET 0
CCU6_CMPSTATH_COUT60PS SET 0
CCU6_CMPSTATH_COUT61PS SET 0
CCU6_CMPSTATH_COUT62PS SET 0
CCU6_CMPSTATH_COUT63PS SET 0
CCU6_CMPSTATH_T13IM SET 0
; RMAP=0 PAGE=3 - CCU6 Compare State Register Low
CCU6_CMPSTATL_CC60ST SET 0
CCU6_CMPSTATL_CC61ST SET 0
CCU6_CMPSTATL_CC62ST SET 0
CCU6_CMPSTATL_CC63ST SET 0
CCU6_CMPSTATL_CCPOS0 SET 0
CCU6_CMPSTATL_CCPOS1 SET 0
CCU6_CMPSTATL_CCPOS2 SET 0
; RMAP=0 PAGE=2 - CCU6 Capture/Compare Interrupt Enable Register High
CCU6_IENH_ENCHE SET 0
CCU6_IENH_ENIDLE SET 0
CCU6_IENH_ENSTR SET 0
CCU6_IENH_ENT13CM SET 0
CCU6_IENH_ENT13PM SET 0
CCU6_IENH_ENTRPF SET 0
CCU6_IENH_ENWHE SET 0
; RMAP=0 PAGE=2 - CCU6 Capture/Compare Interrupt Enable Register Low
CCU6_IENL_ENCC60F SET 0
CCU6_IENL_ENCC60R SET 0
CCU6_IENL_ENCC61F SET 0
CCU6_IENL_ENCC61R SET 0
CCU6_IENL_ENCC62F SET 0
CCU6_IENL_ENCC62R SET 0
CCU6_IENL_ENT12OM SET 0
CCU6_IENL_ENT12PM SET 0
; RMAP=0 PAGE=2 - CCU6 Capture/Compare Interrupt Node Pointer Register High
CCU6_INPH_INPERR SET 0
CCU6_INPH_INPT12 SET 0
CCU6_INPH_INPT13 SET 0
; RMAP=0 PAGE=2 - CCU6 Capture/Compare Interrupt Node Pointer Register Low
CCU6_INPL_INPCC60 SET 0
CCU6_INPL_INPCC61 SET 0
CCU6_INPL_INPCC62 SET 0
CCU6_INPL_INPCHE SET 0
; RMAP=0 PAGE=3 - CCU6 Capture/Compare Interrupt Status Register High
CCU6_ISH_CHE SET 0
CCU6_ISH_IDLE SET 0
CCU6_ISH_STR SET 0
CCU6_ISH_T13CM SET 0
CCU6_ISH_T13PM SET 0
CCU6_ISH_TRPF SET 0
CCU6_ISH_TRPS SET 0
CCU6_ISH_WHE SET 0
; RMAP=0 PAGE=3 - CCU6 Capture/Compare Interrupt Status Register Low
CCU6_ISL_ICC60F SET 0
CCU6_ISL_ICC60R SET 0
CCU6_ISL_ICC61F SET 0
CCU6_ISL_ICC61R SET 0
CCU6_ISL_ICC62F SET 0
CCU6_ISL_ICC62R SET 0
CCU6_ISL_T12OM SET 0
CCU6_ISL_T12PM SET 0
; RMAP=0 PAGE=0 - CCU6 Capture/Compare Interrupt Status Reset Register High
CCU6_ISRH_RCHE SET 0
CCU6_ISRH_RIDLE SET 0
CCU6_ISRH_RSTR SET 0
CCU6_ISRH_RT13CM SET 0
CCU6_ISRH_RT13PM SET 0
CCU6_ISRH_RTRPF SET 0
CCU6_ISRH_RWHE SET 0
; RMAP=0 PAGE=0 - CCU6 Capture/Compare Interrupt Status Reset Register Low
CCU6_ISRL_RCC60F SET 0
CCU6_ISRL_RCC60R SET 0
CCU6_ISRL_RCC61F SET 0
CCU6_ISRL_RCC61R SET 0
CCU6_ISRL_RCC62F SET 0
CCU6_ISRL_RCC62R SET 0
CCU6_ISRL_RT12OM SET 0
CCU6_ISRL_RT12PM SET 0
; RMAP=0 PAGE=2 - CCU6 Capture/Compare Interrupt Status Set Register High
CCU6_ISSH_SCHE SET 0
CCU6_ISSH_SIDLE SET 0
CCU6_ISSH_SSTR SET 0
CCU6_ISSH_ST13CM SET 0
CCU6_ISSH_ST13PM SET 0
CCU6_ISSH_STRPF SET 0
CCU6_ISSH_SWHC SET 0
CCU6_ISSH_SWHE SET 0
; RMAP=0 PAGE=2 - CCU6 Capture/Compare Interrupt Status Set Register Low
CCU6_ISSL_SCC60F SET 0
CCU6_ISSL_SCC60R SET 0
CCU6_ISSL_SCC61F SET 0
CCU6_ISSL_SCC61R SET 0
CCU6_ISSL_SCC62F SET 0
CCU6_ISSL_SCC62R SET 0
CCU6_ISSL_ST12OM SET 0
CCU6_ISSL_ST12PM SET 0
; RMAP=0 PAGE=2 - CCU6 Multi-Channel Mode Control Register
CCU6_MCMCTR_SWSEL SET 0
CCU6_MCMCTR_SWSYN SET 0
; RMAP=0 PAGE=3 - CCU6 Multi-Channel Mode Output Register High
CCU6_MCMOUTH_CURH SET 0
CCU6_MCMOUTH_EXPH SET 0
; RMAP=0 PAGE=3 - CCU6 Multi-Channel Mode Output Register Low
CCU6_MCMOUTL_MCMP SET 0
CCU6_MCMOUTL_R SET 0
; RMAP=0 PAGE=0 - CCU6 Multi-Channel Mode Output Shadow Register High
CCU6_MCMOUTSH_CURHS SET 0
CCU6_MCMOUTSH_EXPHS SET 0
CCU6_MCMOUTSH_STRHP SET 0
; RMAP=0 PAGE=0 - CCU6 Multi-Channel Mode Output Shadow Register Low
CCU6_MCMOUTSL_MCMPS SET 0
CCU6_MCMOUTSL_STRMCM SET 0
; RMAP=0 PAGE=2 - CCU6 Modulation Control Register High
CCU6_MODCTRH_ECT13O SET 0
CCU6_MODCTRH_T13MODEN SET 0
; RMAP=0 PAGE=2 - CCU6 Modulation Control Register Low
CCU6_MODCTRL_MCMEN SET 0
CCU6_MODCTRL_T12MODEN SET 0
; RMAP=0 - CCU6 Page Register
CCU6_PAGE_OP SET 0
CCU6_PAGE_PAGE SET 0
CCU6_PAGE_STNR SET 0
; RMAP=0 PAGE=3 - CCU6 Port Input Select 0 Register High
CCU6_PISEL0H_ISPOS0 SET 0
CCU6_PISEL0H_ISPOS1 SET 0
CCU6_PISEL0H_ISPOS2 SET 0
CCU6_PISEL0H_IST12HR SET 0
; RMAP=0 PAGE=3 - CCU6 Port Input Select 0 Register Low
CCU6_PISEL0L_ISCC60 SET 0
CCU6_PISEL0L_ISCC61 SET 0
CCU6_PISEL0L_ISCC62 SET 0
CCU6_PISEL0L_ISTRP SET 0
; RMAP=0 PAGE=3 - CCU6 Port Input Select 2 Register
CCU6_PISEL2_IST13HR SET 0
; RMAP=0 PAGE=2 - CCU6 Passive State Level Register
CCU6_PSLR_PSL SET 0
CCU6_PSLR_PSL63 SET 0
; RMAP=0 PAGE=1 - CCU6 Dead-Time Control Register for Timer T12 High
CCU6_T12DTCH_DTE0 SET 0
CCU6_T12DTCH_DTE1 SET 0
CCU6_T12DTCH_DTE2 SET 0
CCU6_T12DTCH_DTR0 SET 0
CCU6_T12DTCH_DTR1 SET 0
CCU6_T12DTCH_DTR2 SET 0
; RMAP=0 PAGE=1 - CCU6 Dead-Time Control Register for Timer T12 Low
CCU6_T12DTCL_DTM SET 1
; RMAP=0 PAGE=3 - CCU6 Timer T12 Counter Register High
CCU6_T12H_T12CVH SET 0
; RMAP=0 PAGE=3 - CCU6 Timer T12 Counter Register Low
CCU6_T12L_T12CVL SET 0
; RMAP=0 PAGE=2 - CCU6 Capture/Compare Mode Select Register High
CCU6_T12MSELH_DBYP SET 0
CCU6_T12MSELH_HSYNC SET 0
CCU6_T12MSELH_MSEL62 SET 0
; RMAP=0 PAGE=2 - CCU6 Capture/Compare Mode Select Register Low
CCU6_T12MSELL_MSEL60 SET 0
CCU6_T12MSELL_MSEL61 SET 0
; RMAP=0 PAGE=1 - CCU6 Timer T12 Period Register High
CCU6_T12PRH_T12PVH SET 0
; RMAP=0 PAGE=1 - CCU6 Timer T12 Period Register Low
CCU6_T12PRL_T12PVL SET 1
; RMAP=0 PAGE=3 - CCU6 Timer T13 Counter Register High
CCU6_T13H_T13CVH SET 0
; RMAP=0 PAGE=3 - CCU6 Timer T13 Counter Register Low
CCU6_T13L_T13CVL SET 0
; RMAP=0 PAGE=1 - CCU6 Timer T13 Period Register High
CCU6_T13PRH_T13PVH SET 0
; RMAP=0 PAGE=1 - CCU6 Timer T13 Period Register Low
CCU6_T13PRL_T13PVL SET 1
; RMAP=0 PAGE=1 - CCU6 Timer Control 0 Register High
CCU6_TCTR0H_STE13 SET 0
CCU6_TCTR0H_T13CLK SET 0
CCU6_TCTR0H_T13PRE SET 0
CCU6_TCTR0H_T13R SET 0
; RMAP=0 PAGE=1 - CCU6 Timer Control 0 Register Low
CCU6_TCTR0L_CDIR SET 0
CCU6_TCTR0L_CTM SET 0
CCU6_TCTR0L_STE12 SET 0
CCU6_TCTR0L_T12CLK SET 0
CCU6_TCTR0L_T12PRE SET 0
CCU6_TCTR0L_T12R SET 0
; RMAP=0 PAGE=2 - CCU6 Timer Control 2 Register High
CCU6_TCTR2H_T12RSEL SET 0
CCU6_TCTR2H_T13RSEL SET 0
; RMAP=0 PAGE=2 - CCU6 Timer Control 2 Register Low
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