📄 motfecend.h
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#define MOT_FEC_MII_DATA_OFF 0x0e80 /* MII data register */
#define MOT_FEC_MII_SPEED_OFF 0x0e84 /* MII speed register */
#define MOT_FEC_CSR_REG_OFFSET 0x0e00
/* Control/Status Registers (CSR) bit definitions */
#define MOT_FEC_RX_START_MSK 0xfffffffc /* quad-word alignment */
/* required for rx BDs */
#define MOT_FEC_TX_START_MSK 0xfffffffc /* quad-word alignment */
/* required for tx BDs */
/* Ethernet CSR bit definitions */
#define MOT_FEC_ETH_PINMUX 0x00000004 /* select FEC for port D pins */
#define MOT_FEC_ETH_EN 0x00000002 /* enable Ethernet operation */
#define MOT_FEC_ETH_DIS 0x00000000 /* disable Ethernet operation */
#define MOT_FEC_ETH_RES 0x00000001 /* reset the FEC */
#define MOT_FEC_CTRL_MASK 0x00000007 /* FEC control register mask */
/*
* interrupt bits definitions: these are common to both the
* mask and the event register.
*/
#define MOT_FEC_EVENT_HB 0x80000000 /* heartbeat error */
#define MOT_FEC_EVENT_BABR 0x40000000 /* babbling rx error */
#define MOT_FEC_EVENT_BABT 0x20000000 /* babbling tx error */
#define MOT_FEC_EVENT_GRA 0x10000000 /* graceful stop complete */
#define MOT_FEC_EVENT_TXF 0x08000000 /* tx frame */
#define MOT_FEC_EVENT_TXB 0x04000000 /* tx buffer */
#define MOT_FEC_EVENT_RXF 0x02000000 /* rx frame */
#define MOT_FEC_EVENT_RXB 0x01000000 /* rx buffer */
#define MOT_FEC_EVENT_MII 0x00800000 /* MII transfer */
#define MOT_FEC_EVENT_BERR 0x00400000 /* U-bus access error */
#define MOT_FEC_EVENT_MSK 0xffc00000 /* clear all interrupts */
#define MOT_FEC_MASK_ALL MOT_FEC_EVENT_MSK /* mask all interrupts */
/* bit masks for the interrupt level/vector CSR */
#define MOT_FEC_LVL_MSK 0xe0000000 /* intr level */
#define MOT_FEC_TYPE_MSK 0x0000000c /* highest pending intr */
#define MOT_FEC_VEC_MSK 0xe000000c /* this register mask */
#define MOT_FEC_RES_MSK 0x1ffffff3 /* reserved bits */
#define MOT_FEC_LVL_SHIFT 0x1d /* intr level bits location */
/* transmit and receive active registers definitions */
#define MOT_FEC_TX_ACT 0x01000000 /* tx active bit */
#define MOT_FEC_RX_ACT 0x01000000 /* rx active bit */
/* MII management frame CSRs */
#define MOT_FEC_MII_ST 0x40000000 /* start of frame delimiter */
#define MOT_FEC_MII_OP_RD 0x20000000 /* perform a read operation */
#define MOT_FEC_MII_OP_WR 0x10000000 /* perform a write operation */
#define MOT_FEC_MII_ADDR_MSK 0x0f800000 /* PHY address field mask */
#define MOT_FEC_MII_REG_MSK 0x007c0000 /* PHY register field mask */
#define MOT_FEC_MII_TA 0x00020000 /* turnaround */
#define MOT_FEC_MII_DATA_MSK 0x0000ffff /* PHY data field */
#define MOT_FEC_MII_RA_SHIFT 0x12 /* mii reg address bits */
#define MOT_FEC_MII_PA_SHIFT 0x17 /* mii PHY address bits */
#define MOT_FEC_MII_PRE_DIS 0x00000080 /* desable preamble */
#define MOT_FEC_MII_SPEED_25 0x00000005 /* recommended for 25Mhz CPU */
#define MOT_FEC_MII_SPEED_33 0x00000007 /* recommended for 33Mhz CPU */
#define MOT_FEC_MII_SPEED_40 0x00000008 /* recommended for 40Mhz CPU */
#define MOT_FEC_MII_SPEED_50 0x0000000a /* recommended for 50Mhz CPU */
#define MOT_FEC_MII_SPEED_SHIFT 1 /* MII_SPEED bits location */
#define MOT_FEC_MII_CLOCK_MAX 2500000 /* max freq of MII clock (Hz) */
#define MOT_FEC_MII_MAN_DIS 0x00000000 /* disable the MII management */
/* interface */
#define MOT_FEC_MII_SPEED_MSK 0xffffff81 /* speed field mask */
/* FIFO transmit and receive CSRs definitions */
#define MOT_FEC_FIFO_MSK 0x000003ff /* FIFO rx/tx/bound mask */
/* SDMA function code CSR */
#define MOT_FEC_SDMA_DATA_BE 0x60000000 /* big-endian byte-ordering */
/* for SDMA data transfer */
#define MOT_FEC_SDMA_DATA_PPC 0x20000000 /* PPC byte-ordering */
/* for SDMA data transfer */
#define MOT_FEC_SDMA_DATA_RES 0x00000000 /* reserved value */
#define MOT_FEC_SDMA_BD_BE 0x18000000 /* big-endian byte-ordering */
/* for SDMA BDs transfer */
#define MOT_FEC_SDMA_BD_PPC 0x08000000 /* PPC byte-ordering */
/* for SDMA BDs transfer */
#define MOT_FEC_SDMA_BD_RES 0x00000000 /* reserved value */
#define MOT_FEC_SDMA_FUNC_0 0x00000000 /* no function code */
/* receive control/hash registers bit definitions */
#define MOT_FEC_RX_CTRL_PROM 0x00000008 /* promiscous mode */
#define MOT_FEC_RX_CTRL_MII 0x00000004 /* select MII interface */
#define MOT_FEC_RX_CTRL_DRT 0x00000002 /* disable rx on transmit */
#define MOT_FEC_RX_CTRL_LOOP 0x00000001 /* loopback mode */
#define MOT_FEC_RX_FR_MSK 0x000007ff /* rx frame length mask */
/* transmit control register bit definitions */
#define MOT_FEC_TX_CTRL_FD 0x00000004 /* enable full duplex mode */
#define MOT_FEC_TX_CTRL_HBC 0x00000002 /* HB check is performed */
#define MOT_FEC_TX_CTRL_GRA 0x00000001 /* issue a graceful tx stop */
/* rx/tx buffer descriptors definitions */
#define MOT_FEC_RBD_SZ 8 /* RBD size in byte */
#define MOT_FEC_TBD_SZ 8 /* TBD size in byte */
#define MOT_FEC_TBD_MIN 6 /* min number of TBDs */
#define MOT_FEC_RBD_MIN 4 /* min number of RBDs */
#define MOT_FEC_TBD_POLL_NUM 1 /* one TBD for poll operation */
#define CL_OVERHEAD 4 /* prepended cluster overhead */
#define CL_ALIGNMENT 4 /* cluster required alignment */
#define MBLK_ALIGNMENT 4 /* mBlks required alignment */
#define MOT_FEC_BD_ALIGN 0x10 /* required alignment for RBDs */
#define MOT_FEC_MAX_PCK_SZ (ETHERMTU + SIZEOF_ETHERHEADER \
+ ETHER_CRC_LEN)
#define MOT_FEC_BD_STAT_OFF 0 /* offset of the status word */
#define MOT_FEC_BD_LEN_OFF 2 /* offset of the data length word */
#define MOT_FEC_BD_ADDR_OFF 4 /* offset of the data pointer word */
/* TBD bits definitions */
#define MOT_FEC_TBD_RDY 0x8000 /* ready for transmission */
#define MOT_FEC_TBD_TO1 0x4000 /* transmit ownership bit 1 */
#define MOT_FEC_TBD_WRAP 0x2000 /* look at CSR5 for next bd */
#define MOT_FEC_TBD_TO2 0x1000 /* transmit ownership bit 2 */
#define MOT_FEC_TBD_LAST 0x0800 /* last bd in this frame */
#define MOT_FEC_TBD_CRC 0x0400 /* transmit the CRC sequence */
#define MOT_FEC_TBD_DEF 0x0200 /* deferred transmission */
#define MOT_FEC_TBD_HB 0x0100 /* heartbeat error */
#define MOT_FEC_TBD_LC 0x0080 /* late collision */
#define MOT_FEC_TBD_RL 0x0040 /* retransmission limit */
#define MOT_FEC_TBD_UN 0x0002 /* underrun error */
#define MOT_FEC_TBD_CSL 0x0001 /* carrier sense lost */
#define MOT_FEC_TBD_RC_MASK 0x003c /* retransmission count mask */
/* RBD bits definitions */
#define MOT_FEC_RBD_EMPTY 0x8000 /* ready for reception */
#define MOT_FEC_RBD_RO1 0x4000 /* receive ownership bit 1 */
#define MOT_FEC_RBD_WRAP 0x2000 /* look at CSR4 for next bd */
#define MOT_FEC_RBD_RO2 0x1000 /* receive ownership bit 2 */
#define MOT_FEC_RBD_LAST 0x0800 /* last bd in this frame */
#define MOT_FEC_RBD_RES1 0x0400 /* reserved bit 1 */
#define MOT_FEC_RBD_RES2 0x0200 /* reserved bit 2 */
#define MOT_FEC_RBD_MISS 0x0100 /* address recognition miss */
#define MOT_FEC_RBD_BC 0x0080 /* broadcast frame */
#define MOT_FEC_RBD_MC 0x0040 /* multicast frame */
#define MOT_FEC_RBD_LG 0x0020 /* frame length violation */
#define MOT_FEC_RBD_NO 0x0010 /* nonoctet aligned frame */
#define MOT_FEC_RBD_SH 0x0008 /* short frame error */
/* not supported by the 860T */
#define MOT_FEC_RBD_CRC 0x0004 /* CRC error */
#define MOT_FEC_RBD_OV 0x0002 /* overrun error */
#define MOT_FEC_RBD_TR 0x0001 /* truncated frame (>2KB) */
#define MOT_FEC_RBD_ERR (MOT_FEC_RBD_LG | \
MOT_FEC_RBD_NO | \
MOT_FEC_RBD_CRC | \
MOT_FEC_RBD_OV | \
MOT_FEC_RBD_TR)
#define MOT_FEC_CRC_POLY 0x04c11db7 /* CRC polynomium: */
/* x^32 + x^26 + x^23 + */
/* x^22 + x^16 + x^12 + */
/* x^11 + x^10 + x^8 + */
/* x^7 + x^5 + x^4 + */
/* x^2 + x^1 + x^0 + */
#define MOT_FEC_HASH_MASK 0x7c000000 /* bits 27-31 */
#define MOT_FEC_HASH_SHIFT 0x1a /* to get the index */
/* defines related to the PHY device */
#define MOT_FEC_PHY_PRE_INIT 0x0001 /* PHY info initialized */
#define MOT_FEC_PHY_AUTO 0x0010 /* enable auto-negotiation */
#define MOT_FEC_PHY_TBL 0x0020 /* use negotiation table */
#define MOT_FEC_PHY_100 0x0040 /* PHY may use 100Mbit speed */
#define MOT_FEC_PHY_10 0x0080 /* PHY may use 10Mbit speed */
#define MOT_FEC_PHY_FD 0x0100 /* PHY may use full duplex */
#define MOT_FEC_PHY_HD 0x0200 /* PHY may use half duplex */
#define MOT_FEC_PHY_MAX_WAIT 0x400 /* max delay before */
#define MOT_FEC_PHY_NULL 0xff /* PHY is not present */
#define MOT_FEC_PHY_DEF 0x0 /* PHY's logical address */
/* allowed PHY's speeds */
#define MOT_FEC_100MBS 100000000 /* bits per sec */
#define MOT_FEC_10MBS 10000000 /* bits per sec */
/*
* user flags: full duplex mode, loopback mode, serial interface etc.
* the user may configure some of this options according to his needs
* by setting the related bits in the <userFlags> field of the load string.
*/
#define MOT_FEC_USR_PHY_NO_AN 0x00000001 /* do not auto-negotiate */
#define MOT_FEC_USR_PHY_TBL 0x00000002 /* use negotiation table */
#define MOT_FEC_USR_PHY_NO_FD 0x00000004 /* do not use full duplex */
#define MOT_FEC_USR_PHY_NO_100 0x00000008 /* do not use 100Mbit speed */
#define MOT_FEC_USR_PHY_NO_HD 0x00000010 /* do not use half duplex */
#define MOT_FEC_USR_PHY_NO_10 0x00000020 /* do not use 10Mbit speed */
#define MOT_FEC_USR_PHY_ISO 0x00000100 /* isolate a PHY */
#define MOT_FEC_USR_SER 0x00000200 /* 7-wire serial interface */
#define MOT_FEC_USR_LOOP 0x00000400 /* loopback mode */
/* only use it for testing */
#define MOT_FEC_USR_HBC 0x00000080 /* perform heartbeat control */
#define MOT_FEC_TBD_OK 0x1 /* the TBD is a good one */
#define MOT_FEC_TBD_BUSY 0x2 /* the TBD has not been used */
#define MOT_FEC_TBD_ERROR 0x4 /* the TBD is errored */
#define PKT_TYPE_MULTI 0x1 /* packet with a multicast address */
#define PKT_TYPE_UNI 0x2 /* packet with a unicast address */
#define PKT_TYPE_NONE 0x4 /* address type is not meaningful */
#define BUF_TYPE_CL 0x1 /* this's a cluster pointer */
#define BUF_TYPE_MBLK 0x2 /* this's a mblk pointer */
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