divider.fit.eqn

这个是用vhdl语言编写的除法器,仅仅供大家参考.

--operation mode is normal

A1L1 = A1L88Q & count2[1] & !count2[0];

--A1L2 is add_op~31 at LC3_J40
--operation mode is normal

A1L2 = A1L88Q & count2[1] & !count2[0];


--A1L8 is carries[0]~359 at LC1_J40
--operation mode is normal

A1L8 = drreg[0] & A1L97Q # !drreg[0] & (!A1L1);

--A1L9 is carries[0]~361 at LC1_J40
--operation mode is normal

A1L9 = drreg[0] & A1L97Q # !drreg[0] & (!A1L1);


--drreg[1] is drreg[1] at LC2_J42
--operation mode is normal

drreg[1]_lut_out = divisor[1];
drreg[1] = DFFEA(drreg[1]_lut_out, GLOBAL(clock), , , A1L93, , );

--A1L73Q is drreg[1]~10 at LC2_J42
--operation mode is normal

A1L73Q = drreg[1];


--A1L721 is tcbuffout[1]~54 at LC2_J41
--operation mode is normal

A1L721 = drreg[1] $ (!count2[0] & A1L88Q & count2[1]);

--A1L821 is tcbuffout[1]~56 at LC2_J41
--operation mode is normal

A1L821 = drreg[1] $ (!count2[0] & A1L88Q & count2[1]);


--A1L01 is carries[1]~360 at LC4_J41
--operation mode is normal

A1L01 = A1L28Q & (A1L8 # !A1L721) # !A1L28Q & A1L8 & !A1L721;

--A1L11 is carries[1]~362 at LC4_J41
--operation mode is normal

A1L11 = A1L28Q & (A1L8 # !A1L721) # !A1L28Q & A1L8 & !A1L721;


--drreg[3] is drreg[3] at LC7_J42
--operation mode is normal

drreg[3]_lut_out = divisor[3];
drreg[3] = DFFEA(drreg[3]_lut_out, GLOBAL(clock), , , A1L93, , );

--A1L34Q is drreg[3]~11 at LC7_J42
--operation mode is normal

A1L34Q = drreg[3];


--A1L5 is adderout[3]~354 at LC3_J42
--operation mode is normal

A1L5 = drreg[3] $ (A1L88Q & (count2[0] # !count2[1]));

--A1L6 is adderout[3]~355 at LC3_J42
--operation mode is normal

A1L6 = drreg[3] $ (A1L88Q & (count2[0] # !count2[1]));


--adderout[3] is adderout[3] at LC6_J41
--operation mode is normal

adderout[3] = A1L5 $ (A1L921 & A1L01 & A1L58Q # !A1L921 & (A1L01 # A1L58Q));

--A1L7 is adderout[3]~356 at LC6_J41
--operation mode is normal

A1L7 = A1L5 $ (A1L921 & A1L01 & A1L58Q # !A1L921 & (A1L01 # A1L58Q));


--A1L701 is remainder~2115 at LC2_J40
--operation mode is normal

A1L701 = count2[1] & (count2[0] # !A1L88Q);

--A1L811 is remainder~2142 at LC2_J40
--operation mode is normal

A1L811 = count2[1] & (count2[0] # !A1L88Q);


--A1L801 is remainder~2116 at LC4_J40
--operation mode is normal

A1L801 = A1L701 & (A1L16 & A1L67Q # !A1L16 & (A1L97Q));

--A1L911 is remainder~2143 at LC4_J40
--operation mode is normal

A1L911 = A1L701 & (A1L16 & A1L67Q # !A1L16 & (A1L97Q));


--A1L901 is remainder~2117 at LC8_J40
--operation mode is normal

A1L901 = A1L801 # A1L601 & (A1L97Q $ drreg[0]);

--A1L021 is remainder~2144 at LC8_J40
--operation mode is normal

A1L021 = A1L801 # A1L601 & (A1L97Q $ drreg[0]);


--A1L011 is remainder~2119 at LC6_J40
--operation mode is normal

A1L011 = A1L16 & (!A1L97Q) # !A1L16 & !A1L28Q # !A1L701;

--A1L121 is remainder~2145 at LC6_J40
--operation mode is normal

A1L121 = A1L16 & (!A1L97Q) # !A1L16 & !A1L28Q # !A1L701;

--A1L221 is remainder~2146 at LC6_J40
--operation mode is normal

A1L221 = A1L16 & (!A1L97Q) # !A1L16 & !A1L28Q # !A1L701;


--A1L211 is remainder~2125 at LC7_J40
--operation mode is normal

A1L211 = (A1L8 $ A1L28Q $ A1L721 # !A1L601) & CASCADE(A1L221);

--A1L321 is remainder~2147 at LC7_J40
--operation mode is normal

A1L321 = (A1L8 $ A1L28Q $ A1L721 # !A1L601) & CASCADE(A1L221);


--A1L111 is remainder~2121 at LC7_J41
--operation mode is normal

A1L111 = A1L16 & (!A1L28Q) # !A1L16 & !A1L58Q # !A1L701;

--A1L421 is remainder~2148 at LC7_J41
--operation mode is normal

A1L421 = A1L16 & (!A1L28Q) # !A1L16 & !A1L58Q # !A1L701;

--A1L521 is remainder~2149 at LC7_J41
--operation mode is normal

A1L521 = A1L16 & (!A1L28Q) # !A1L16 & !A1L58Q # !A1L701;


--A1L311 is remainder~2126 at LC8_J41
--operation mode is normal

A1L311 = (A1L01 $ A1L58Q $ A1L921 # !A1L601) & CASCADE(A1L521);

--A1L621 is remainder~2150 at LC8_J41
--operation mode is normal

A1L621 = (A1L01 $ A1L58Q $ A1L921 # !A1L601) & CASCADE(A1L521);


--A1L93 is drreg[2]~4 at LC8_J42
--operation mode is normal

A1L93 = !A1L06;

--A1L14 is drreg[2]~12 at LC8_J42
--operation mode is normal

A1L14 = !A1L06;


--clock is clock at PIN_79
--operation mode is input

clock = INPUT();


--dividend[0] is dividend[0] at PIN_67
--operation mode is input

dividend[0] = INPUT();


--dividend[1] is dividend[1] at PIN_68
--operation mode is input

dividend[1] = INPUT();


--dividend[2] is dividend[2] at PIN_69
--operation mode is input

dividend[2] = INPUT();


--divisor[2] is divisor[2] at PIN_55
--operation mode is input

divisor[2] = INPUT();


--dividend[3] is dividend[3] at PIN_70
--operation mode is input

dividend[3] = INPUT();


--divisor[0] is divisor[0] at PIN_53
--operation mode is input

divisor[0] = INPUT();


--divisor[1] is divisor[1] at PIN_54
--operation mode is input

divisor[1] = INPUT();


--divisor[3] is divisor[3] at PIN_56
--operation mode is input

divisor[3] = INPUT();


--quotient[0] is quotient[0] at PIN_7
--operation mode is output

quotient[0] = OUTPUT(A1L25);


--quotient[1] is quotient[1] at PIN_8
--operation mode is output

quotient[1] = OUTPUT(A1L35);


--quotient[2] is quotient[2] at PIN_9
--operation mode is output

quotient[2] = OUTPUT(A1L45);


--quotient[3] is quotient[3] at PIN_11
--operation mode is output

quotient[3] = OUTPUT(A1L55);


--remainder_r[0] is remainder_r[0] at PIN_12
--operation mode is output

remainder_r[0] = OUTPUT(A1L79);


--remainder_r[1] is remainder_r[1] at PIN_13
--operation mode is output

remainder_r[1] = OUTPUT(A1L89);


--remainder_r[2] is remainder_r[2] at PIN_14
--operation mode is output

remainder_r[2] = OUTPUT(A1L99);


--remainder_r[3] is remainder_r[3] at PIN_15
--operation mode is output

remainder_r[3] = OUTPUT(GND);


--remainder[0] is remainder[0] at PIN_111
--operation mode is bidir

remainder[0]_tri_out = TRI(A1L76Q, VCC);
remainder[0] = BIDIR(remainder[0]_tri_out);


--remainder[1] is remainder[1] at PIN_112
--operation mode is bidir

remainder[1]_tri_out = TRI(A1L07Q, VCC);
remainder[1] = BIDIR(remainder[1]_tri_out);


--remainder[2] is remainder[2] at PIN_113
--operation mode is bidir

remainder[2]_tri_out = TRI(A1L37Q, VCC);
remainder[2] = BIDIR(remainder[2]_tri_out);


--remainder[3] is remainder[3] at PIN_114
--operation mode is bidir

remainder[3]_tri_out = TRI(A1L67Q, VCC);
remainder[3] = BIDIR(remainder[3]_tri_out);


--remainder[4] is remainder[4] at PIN_115
--operation mode is bidir

remainder[4]_tri_out = TRI(A1L97Q, VCC);
remainder[4] = BIDIR(remainder[4]_tri_out);


--remainder[5] is remainder[5] at PIN_116
--operation mode is bidir

remainder[5]_tri_out = TRI(A1L28Q, VCC);
remainder[5] = BIDIR(remainder[5]_tri_out);


--remainder[6] is remainder[6] at PIN_119
--operation mode is bidir

remainder[6]_tri_out = TRI(A1L58Q, VCC);
remainder[6] = BIDIR(remainder[6]_tri_out);


--remainder[7] is remainder[7] at PIN_120
--operation mode is bidir

remainder[7]_tri_out = TRI(A1L88Q, VCC);
remainder[7] = BIDIR(remainder[7]_tri_out);


--remainder[8] is remainder[8] at PIN_39
--operation mode is bidir

remainder[8]_tri_out = TRI(A1L19Q, VCC);
remainder[8] = BIDIR(remainder[8]_tri_out);


--finish is finish at PIN_193
--operation mode is bidir

finish_tri_out = TRI(A1L64Q, VCC);
finish = BIDIR(finish_tri_out);