divider.fit.eqn

这个是用vhdl语言编写的除法器,仅仅供大家参考.

-- Copyright (C) 1991-2005 Altera Corporation
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-- and other software and tools, and its AMPP partner logic 
-- functions, and any output files any of the foregoing 
-- (including device programming or simulation files), and any 
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-- Subscription Agreement, Altera MegaCore Function License 
-- Agreement, or other applicable license agreement, including, 
-- without limitation, that your use is for the sole purpose of 
-- programming logic devices manufactured by Altera and sold by 
-- Altera or its authorized distributors.  Please refer to the 
-- applicable agreement for further details.
--A1L76Q is remainder[0]~reg0 at LC5_J42
--operation mode is normal

A1L76Q_lut_out = A1L06 & (A1L16 & A1L19Q # !A1L16 & (A1L76Q));
A1L76Q = DFFEA(A1L76Q_lut_out, GLOBAL(clock), , , , , );

--A1L66Q is remainder[0]~2129 at LC5_J42
--operation mode is normal

A1L66Q = A1L76Q;


--A1L64Q is finish~reg0 at LC4_J38
--operation mode is normal

A1L64Q_lut_out = count[1] & count[0] & count2[1] & count2[0];
A1L64Q = DFFEA(A1L64Q_lut_out, GLOBAL(clock), , , , , );

--A1L54Q is finish~2 at LC4_J38
--operation mode is normal

A1L54Q = A1L64Q;


--A1L25 is quotient~41 at LC1_A52
--operation mode is normal

A1L25 = A1L76Q & A1L64Q;

--A1L65 is quotient~45 at LC1_A52
--operation mode is normal

A1L65 = A1L76Q & A1L64Q;


--A1L07Q is remainder[1]~reg0 at LC4_J39
--operation mode is normal

A1L07Q_lut_out = count2[1] & A1L301 # !count2[1] & (count2[0] & A1L301 # !count2[0] & (dividend[0]));
A1L07Q = DFFEA(A1L07Q_lut_out, GLOBAL(clock), , , , , );

--A1L96Q is remainder[1]~2130 at LC4_J39
--operation mode is normal

A1L96Q = A1L07Q;


--A1L35 is quotient~42 at LC2_J43
--operation mode is normal

A1L35 = A1L64Q & A1L07Q;

--A1L75 is quotient~46 at LC2_J43
--operation mode is normal

A1L75 = A1L64Q & A1L07Q;


--A1L37Q is remainder[2]~reg0 at LC5_J39
--operation mode is normal

A1L37Q_lut_out = count2[1] & A1L401 # !count2[1] & (count2[0] & A1L401 # !count2[0] & (dividend[1]));
A1L37Q = DFFEA(A1L37Q_lut_out, GLOBAL(clock), , , , , );

--A1L27Q is remainder[2]~2131 at LC5_J39
--operation mode is normal

A1L27Q = A1L37Q;


--A1L45 is quotient~43 at LC4_A52
--operation mode is normal

A1L45 = A1L64Q & A1L37Q;

--A1L85 is quotient~47 at LC4_A52
--operation mode is normal

A1L85 = A1L64Q & A1L37Q;


--A1L67Q is remainder[3]~reg0 at LC1_J39
--operation mode is normal

A1L67Q_lut_out = count2[1] & A1L501 # !count2[1] & (count2[0] & A1L501 # !count2[0] & (dividend[2]));
A1L67Q = DFFEA(A1L67Q_lut_out, GLOBAL(clock), , , , , );

--A1L57Q is remainder[3]~2132 at LC1_J39
--operation mode is normal

A1L57Q = A1L67Q;


--A1L55 is quotient~44 at LC1_J43
--operation mode is normal

A1L55 = A1L64Q & A1L67Q;

--A1L95 is quotient~48 at LC1_J43
--operation mode is normal

A1L95 = A1L64Q & A1L67Q;


--A1L28Q is remainder[5]~reg0 at LC5_J43
--operation mode is normal

A1L28Q_lut_out = !A1L211;
A1L28Q = DFFEA(A1L28Q_lut_out, GLOBAL(clock), , , , , );

--A1L18Q is remainder[5]~2133 at LC5_J43
--operation mode is normal

A1L18Q = A1L28Q;


--A1L79 is remainder_r~27 at LC4_J43
--operation mode is normal

A1L79 = A1L64Q & A1L28Q;

--A1L001 is remainder_r~30 at LC4_J43
--operation mode is normal

A1L001 = A1L64Q & A1L28Q;


--A1L58Q is remainder[6]~reg0 at LC5_J41
--operation mode is normal

A1L58Q_lut_out = !A1L311;
A1L58Q = DFFEA(A1L58Q_lut_out, GLOBAL(clock), , , , , );

--A1L48Q is remainder[6]~2134 at LC5_J41
--operation mode is normal

A1L48Q = A1L58Q;


--A1L89 is remainder_r~28 at LC8_J43
--operation mode is normal

A1L89 = A1L64Q & A1L58Q;

--A1L101 is remainder_r~31 at LC8_J43
--operation mode is normal

A1L101 = A1L64Q & A1L58Q;


--A1L88Q is remainder[7]~reg0 at LC1_J41
--operation mode is normal

A1L88Q_lut_out = A1L58Q & (A1L16 # A1L601 & !adderout[3]) # !A1L58Q & (A1L601 & !adderout[3]);
A1L88Q = DFFEA(A1L88Q_lut_out, GLOBAL(clock), , , , , );

--A1L78Q is remainder[7]~2135 at LC1_J41
--operation mode is normal

A1L78Q = A1L88Q;


--A1L99 is remainder_r~29 at LC3_J43
--operation mode is normal

A1L99 = A1L64Q & A1L88Q;

--A1L201 is remainder_r~32 at LC3_J43
--operation mode is normal

A1L201 = A1L64Q & A1L88Q;


--count2[1] is count2[1] at LC1_J38
--operation mode is normal

count2[1]_lut_out = count2[1] $ count2[0];
count2[1] = DFFEA(count2[1]_lut_out, GLOBAL(clock), , , , , );

--A1L81Q is count2[1]~44 at LC1_J38
--operation mode is normal

A1L81Q = count2[1];


--count2[0] is count2[0] at LC8_J38
--operation mode is normal

count2[0]_lut_out = count2[1] & (!count[0] # !count[1]) # !count2[0];
count2[0] = DFFEA(count2[0]_lut_out, GLOBAL(clock), , , , , );

--A1L61Q is count2[0]~45 at LC8_J38
--operation mode is normal

A1L61Q = count2[0];


--A1L06 is reduce_nor~40 at LC6_J42
--operation mode is normal

A1L06 = count2[1] # count2[0];

--A1L26 is reduce_nor~42 at LC6_J42
--operation mode is normal

A1L26 = count2[1] # count2[0];


--A1L19Q is remainder[8]~reg0 at LC2_J38
--operation mode is normal

A1L19Q_lut_out = count2[0] & (count2[1] $ !A1L88Q) # !count2[0] & count2[1] & !A1L88Q & A1L19Q;
A1L19Q = DFFEA(A1L19Q_lut_out, GLOBAL(clock), , , , , );

--A1L09Q is remainder[8]~2136 at LC2_J38
--operation mode is normal

A1L09Q = A1L19Q;


--A1L16 is reduce_nor~41 at LC6_J38
--operation mode is normal

A1L16 = count2[1] & count2[0];

--A1L36 is reduce_nor~43 at LC6_J38
--operation mode is normal

A1L36 = count2[1] & count2[0];


--count[1] is count[1] at LC5_J38
--operation mode is normal

count[1]_lut_out = count[1] $ (count[0] & count2[1] & count2[0]);
count[1] = DFFEA(count[1]_lut_out, GLOBAL(clock), , , , , );

--A1L22Q is count[1]~18 at LC5_J38
--operation mode is normal

A1L22Q = count[1];


--count[0] is count[0] at LC7_J38
--operation mode is normal

count[0]_lut_out = count[0] $ (count2[1] & count2[0]);
count[0] = DFFEA(count[0]_lut_out, GLOBAL(clock), , , , , );

--A1L02Q is count[0]~19 at LC7_J38
--operation mode is normal

A1L02Q = count[0];


--A1L301 is remainder~2098 at LC2_J39
--operation mode is normal

A1L301 = count2[1] & (count2[0] & A1L76Q # !count2[0] & (A1L07Q)) # !count2[1] & (A1L07Q);

--A1L411 is remainder~2137 at LC2_J39
--operation mode is normal

A1L411 = count2[1] & (count2[0] & A1L76Q # !count2[0] & (A1L07Q)) # !count2[1] & (A1L07Q);


--A1L401 is remainder~2100 at LC3_J39
--operation mode is normal

A1L401 = count2[1] & (count2[0] & A1L07Q # !count2[0] & (A1L37Q)) # !count2[1] & (A1L37Q);

--A1L511 is remainder~2138 at LC3_J39
--operation mode is normal

A1L511 = count2[1] & (count2[0] & A1L07Q # !count2[0] & (A1L37Q)) # !count2[1] & (A1L37Q);


--A1L501 is remainder~2102 at LC6_J39
--operation mode is normal

A1L501 = count2[1] & (count2[0] & A1L37Q # !count2[0] & (A1L67Q)) # !count2[1] & (A1L67Q);

--A1L611 is remainder~2139 at LC6_J39
--operation mode is normal

A1L611 = count2[1] & (count2[0] & A1L37Q # !count2[0] & (A1L67Q)) # !count2[1] & (A1L67Q);


--A1L601 is remainder~2106 at LC3_J38
--operation mode is normal

A1L601 = count2[0] & (!count2[1]) # !count2[0] & A1L88Q & count2[1];

--A1L711 is remainder~2140 at LC3_J38
--operation mode is normal

A1L711 = count2[0] & (!count2[1]) # !count2[0] & A1L88Q & count2[1];


--drreg[2] is drreg[2] at LC4_J42
--operation mode is normal

drreg[2]_lut_out = divisor[2];
drreg[2] = DFFEA(drreg[2]_lut_out, GLOBAL(clock), , , A1L93, , );

--A1L04Q is drreg[2]~8 at LC4_J42
--operation mode is normal

A1L04Q = drreg[2];


--A1L921 is tcbuffout[2]~53 at LC3_J41
--operation mode is normal

A1L921 = drreg[2] $ (!count2[0] & A1L88Q & count2[1]);

--A1L031 is tcbuffout[2]~55 at LC3_J41
--operation mode is normal

A1L031 = drreg[2] $ (!count2[0] & A1L88Q & count2[1]);


--A1L97Q is remainder[4]~reg0 at LC5_J40
--operation mode is normal

A1L97Q_lut_out = A1L901 # dividend[3] & !count2[1] & !count2[0];
A1L97Q = DFFEA(A1L97Q_lut_out, GLOBAL(clock), , , , , );

--A1L87Q is remainder[4]~2141 at LC5_J40
--operation mode is normal

A1L87Q = A1L97Q;


--drreg[0] is drreg[0] at LC1_J42
--operation mode is normal

drreg[0]_lut_out = divisor[0];
drreg[0] = DFFEA(drreg[0]_lut_out, GLOBAL(clock), , , A1L93, , );

--A1L53Q is drreg[0]~9 at LC1_J42
--operation mode is normal

A1L53Q = drreg[0];


--A1L1 is add_op~30 at LC3_J40