📄 divider.tan.qmsg
字号:
{ "Info" "IDAT_DAT_COMPLETED" "" "Info: Delay annotation completed successfully" { } { } 0}
{ "Warning" "WTAN_NO_CLOCKS" "" "Warning: Found pins functioning as undefined clocks and/or memory enables" { { "Info" "ITAN_NODE_MAP_TO_CLK" "clock " "Info: Assuming node \"clock\" is an undefined clock" { } { { "divider.vhd" "" { Text "E:/workroom/产品/开放式CPU实验教学系统TEC-CA/TEC-CA出厂光盘/实验/7-divider/divider.vhd" 10 -1 0 } } { "c:/altera/quartus50/bin/Assignment Editor.qase" "" { Assignment "c:/altera/quartus50/bin/Assignment Editor.qase" 1 { { 0 "clock" } } } } } 0} } { } 0}
{ "Info" "ITDB_FULL_CLOCK_REG_RESULT" "clock register remainder\[7\]~reg0 register remainder\[6\]~reg0 74.63 MHz 13.4 ns Internal " "Info: Clock \"clock\" has Internal fmax of 74.63 MHz between source register \"remainder\[7\]~reg0\" and destination register \"remainder\[6\]~reg0\" (period= 13.4 ns)" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "11.600 ns + Longest register register " "Info: + Longest register to register delay is 11.600 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns remainder\[7\]~reg0 1 REG LC1_J41 9 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC1_J41; Fanout = 9; REG Node = 'remainder\[7\]~reg0'" { } { { "E:/workroom/产品/开放式CPU实验教学系统TEC-CA/TEC-CA出厂光盘/实验/7-divider/db/divider_cmp.qrpt" "" { Report "E:/workroom/产品/开放式CPU实验教学系统TEC-CA/TEC-CA出厂光盘/实验/7-divider/db/divider_cmp.qrpt" Compiler "divider" "UNKNOWN" "V1" "E:/workroom/产品/开放式CPU实验教学系统TEC-CA/TEC-CA出厂光盘/实验/7-divider/db/divider.quartus_db" { Floorplan "E:/workroom/产品/开放式CPU实验教学系统TEC-CA/TEC-CA出厂光盘/实验/7-divider/" "" "" { remainder[7]~reg0 } "NODE_NAME" } "" } } { "divider.vhd" "" { Text "E:/workroom/产品/开放式CPU实验教学系统TEC-CA/TEC-CA出厂光盘/实验/7-divider/divider.vhd" 64 -1 0 } } } 0} { "Info" "ITDB_NODE_DELAY" "IC(1.100 ns) + CELL(2.000 ns) 3.100 ns add_op~30 2 COMB LC3_J40 1 " "Info: 2: + IC(1.100 ns) + CELL(2.000 ns) = 3.100 ns; Loc. = LC3_J40; Fanout = 1; COMB Node = 'add_op~30'" { } { { "E:/workroom/产品/开放式CPU实验教学系统TEC-CA/TEC-CA出厂光盘/实验/7-divider/db/divider_cmp.qrpt" "" { Report "E:/workroom/产品/开放式CPU实验教学系统TEC-CA/TEC-CA出厂光盘/实验/7-divider/db/divider_cmp.qrpt" Compiler "divider" "UNKNOWN" "V1" "E:/workroom/产品/开放式CPU实验教学系统TEC-CA/TEC-CA出厂光盘/实验/7-divider/db/divider.quartus_db" { Floorplan "E:/workroom/产品/开放式CPU实验教学系统TEC-CA/TEC-CA出厂光盘/实验/7-divider/" "" "3.100 ns" { remainder[7]~reg0 add_op~30 } "NODE_NAME" } "" } } { "divider.vhd" "" { Text "E:/workroom/产品/开放式CPU实验教学系统TEC-CA/TEC-CA出厂光盘/实验/7-divider/divider.vhd" 31 -1 0 } } } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.200 ns) + CELL(1.700 ns) 5.000 ns carries\[0\]~359 3 COMB LC1_J40 2 " "Info: 3: + IC(0.200 ns) + CELL(1.700 ns) = 5.000 ns; Loc. = LC1_J40; Fanout = 2; COMB Node = 'carries\[0\]~359'" { } { { "E:/workroom/产品/开放式CPU实验教学系统TEC-CA/TEC-CA出厂光盘/实验/7-divider/db/divider_cmp.qrpt" "" { Report "E:/workroom/产品/开放式CPU实验教学系统TEC-CA/TEC-CA出厂光盘/实验/7-divider/db/divider_cmp.qrpt" Compiler "divider" "UNKNOWN" "V1" "E:/workroom/产品/开放式CPU实验教学系统TEC-CA/TEC-CA出厂光盘/实验/7-divider/db/divider.quartus_db" { Floorplan "E:/workroom/产品/开放式CPU实验教学系统TEC-CA/TEC-CA出厂光盘/实验/7-divider/" "" "1.900 ns" { add_op~30 carries[0]~359 } "NODE_NAME" } "" } } { "divider.vhd" "" { Text "E:/workroom/产品/开放式CPU实验教学系统TEC-CA/TEC-CA出厂光盘/实验/7-divider/divider.vhd" 22 -1 0 } } } 0} { "Info" "ITDB_NODE_DELAY" "IC(1.100 ns) + CELL(1.900 ns) 8.000 ns carries\[1\]~360 4 COMB LC4_J41 2 " "Info: 4: + IC(1.100 ns) + CELL(1.900 ns) = 8.000 ns; Loc. = LC4_J41; Fanout = 2; COMB Node = 'carries\[1\]~360'" { } { { "E:/workroom/产品/开放式CPU实验教学系统TEC-CA/TEC-CA出厂光盘/实验/7-divider/db/divider_cmp.qrpt" "" { Report "E:/workroom/产品/开放式CPU实验教学系统TEC-CA/TEC-CA出厂光盘/实验/7-divider/db/divider_cmp.qrpt" Compiler "divider" "UNKNOWN" "V1" "E:/workroom/产品/开放式CPU实验教学系统TEC-CA/TEC-CA出厂光盘/实验/7-divider/db/divider.quartus_db" { Floorplan "E:/workroom/产品/开放式CPU实验教学系统TEC-CA/TEC-CA出厂光盘/实验/7-divider/" "" "3.000 ns" { carries[0]~359 carries[1]~360 } "NODE_NAME" } "" } } { "divider.vhd" "" { Text "E:/workroom/产品/开放式CPU实验教学系统TEC-CA/TEC-CA出厂光盘/实验/7-divider/divider.vhd" 22 -1 0 } } } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.200 ns) + CELL(2.200 ns) 10.400 ns remainder~2126 5 COMB LC8_J41 1 " "Info: 5: + IC(0.200 ns) + CELL(2.200 ns) = 10.400 ns; Loc. = LC8_J41; Fanout = 1; COMB Node = 'remainder~2126'" { } { { "E:/workroom/产品/开放式CPU实验教学系统TEC-CA/TEC-CA出厂光盘/实验/7-divider/db/divider_cmp.qrpt" "" { Report "E:/workroom/产品/开放式CPU实验教学系统TEC-CA/TEC-CA出厂光盘/实验/7-divider/db/divider_cmp.qrpt" Compiler "divider" "UNKNOWN" "V1" "E:/workroom/产品/开放式CPU实验教学系统TEC-CA/TEC-CA出厂光盘/实验/7-divider/db/divider.quartus_db" { Floorplan "E:/workroom/产品/开放式CPU实验教学系统TEC-CA/TEC-CA出厂光盘/实验/7-divider/" "" "2.400 ns" { carries[1]~360 remainder~2126 } "NODE_NAME" } "" } } { "divider.vhd" "" { Text "E:/workroom/产品/开放式CPU实验教学系统TEC-CA/TEC-CA出厂光盘/实验/7-divider/divider.vhd" 13 -1 0 } } } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.200 ns) + CELL(1.000 ns) 11.600 ns remainder\[6\]~reg0 6 REG LC5_J41 6 " "Info: 6: + IC(0.200 ns) + CELL(1.000 ns) = 11.600 ns; Loc. = LC5_J41; Fanout = 6; REG Node = 'remainder\[6\]~reg0'" { } { { "E:/workroom/产品/开放式CPU实验教学系统TEC-CA/TEC-CA出厂光盘/实验/7-divider/db/divider_cmp.qrpt" "" { Report "E:/workroom/产品/开放式CPU实验教学系统TEC-CA/TEC-CA出厂光盘/实验/7-divider/db/divider_cmp.qrpt" Compiler "divider" "UNKNOWN" "V1" "E:/workroom/产品/开放式CPU实验教学系统TEC-CA/TEC-CA出厂光盘/实验/7-divider/db/divider.quartus_db" { Floorplan "E:/workroom/产品/开放式CPU实验教学系统TEC-CA/TEC-CA出厂光盘/实验/7-divider/" "" "1.200 ns" { remainder~2126 remainder[6]~reg0 } "NODE_NAME" } "" } } { "divider.vhd" "" { Text "E:/workroom/产品/开放式CPU实验教学系统TEC-CA/TEC-CA出厂光盘/实验/7-divider/divider.vhd" 64 -1 0 } } } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "8.800 ns 75.86 % " "Info: Total cell delay = 8.800 ns ( 75.86 % )" { } { } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "2.800 ns 24.14 % " "Info: Total interconnect delay = 2.800 ns ( 24.14 % )" { } { } 0} } { { "E:/workroom/产品/开放式CPU实验教学系统TEC-CA/TEC-CA出厂光盘/实验/7-divider/db/divider_cmp.qrpt" "" { Report "E:/workroom/产品/开放式CPU实验教学系统TEC-CA/TEC-CA出厂光盘/实验/7-divider/db/divider_cmp.qrpt" Compiler "divider" "UNKNOWN" "V1" "E:/workroom/产品/开放式CPU实验教学系统TEC-CA/TEC-CA出厂光盘/实验/7-divider/db/divider.quartus_db" { Floorplan "E:/workroom/产品/开放式CPU实验教学系统TEC-CA/TEC-CA出厂光盘/实验/7-divider/" "" "11.600 ns" { remainder[7]~reg0 add_op~30 carries[0]~359 carries[1]~360 remainder~2126 remainder[6]~reg0 } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "11.600 ns" { remainder[7]~reg0 add_op~30 carries[0]~359 carries[1]~360 remainder~2126 remainder[6]~reg0 } { 0.000ns 1.100ns 0.200ns 1.100ns 0.200ns 0.200ns } { 0.000ns 2.000ns 1.700ns 1.900ns 2.200ns 1.000ns } } } } 0} { "Info" "ITDB_FULL_CLOCK_SKEW_RESULT" "0.000 ns - Smallest " "Info: - Smallest clock skew is 0.000 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clock destination 1.900 ns + Shortest register " "Info: + Shortest clock path from clock \"clock\" to destination register is 1.900 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.500 ns) 0.500 ns clock 1 CLK PIN_79 18 " "Info: 1: + IC(0.000 ns) + CELL(0.500 ns) = 0.500 ns; Loc. = PIN_79; Fanout = 18; CLK Node = 'clock'" { } { { "E:/workroom/产品/开放式CPU实验教学系统TEC-CA/TEC-CA出厂光盘/实验/7-divider/db/divider_cmp.qrpt" "" { Report "E:/workroom/产品/开放式CPU实验教学系统TEC-CA/TEC-CA出厂光盘/实验/7-divider/db/divider_cmp.qrpt" Compiler "divider" "UNKNOWN" "V1" "E:/workroom/产品/开放式CPU实验教学系统TEC-CA/TEC-CA出厂光盘/实验/7-divider/db/divider.quartus_db" { Floorplan "E:/workroom/产品/开放式CPU实验教学系统TEC-CA/TEC-CA出厂光盘/实验/7-divider/" "" "" { clock } "NODE_NAME" } "" } } { "divider.vhd" "" { Text "E:/workroom/产品/开放式CPU实验教学系统TEC-CA/TEC-CA出厂光盘/实验/7-divider/divider.vhd" 10 -1 0 } } } 0} { "Info" "ITDB_NODE_DELAY" "IC(1.400 ns) + CELL(0.000 ns) 1.900 ns remainder\[6\]~reg0 2 REG LC5_J41 6 " "Info: 2: + IC(1.400 ns) + CELL(0.000 ns) = 1.900 ns; Loc. = LC5_J41; Fanout = 6; REG Node = 'remainder\[6\]~reg0'" { } { { "E:/workroom/产品/开放式CPU实验教学系统TEC-CA/TEC-CA出厂光盘/实验/7-divider/db/divider_cmp.qrpt" "" { Report "E:/workroom/产品/开放式CPU实验教学系统TEC-CA/TEC-CA出厂光盘/实验/7-divider/db/divider_cmp.qrpt" Compiler "divider" "UNKNOWN" "V1" "E:/workroom/产品/开放式CPU实验教学系统TEC-CA/TEC-CA出厂光盘/实验/7-divider/db/divider.quartus_db" { Floorplan "E:/workroom/产品/开放式CPU实验教学系统TEC-CA/TEC-CA出厂光盘/实验/7-divider/" "" "1.400 ns" { clock remainder[6]~reg0 } "NODE_NAME" } "" } } { "divider.vhd" "" { Text "E:/workroom/产品/开放式CPU实验教学系统TEC-CA/TEC-CA出厂光盘/实验/7-divider/divider.vhd" 64 -1 0 } } } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "0.500 ns 26.32 % " "Info: Total cell delay = 0.500 ns ( 26.32 % )" { } { } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.400 ns 73.68 % " "Info: Total interconnect delay = 1.400 ns ( 73.68 % )" { } { } 0} } { { "E:/workroom/产品/开放式CPU实验教学系统TEC-CA/TEC-CA出厂光盘/实验/7-divider/db/divider_cmp.qrpt" "" { Report "E:/workroom/产品/开放式CPU实验教学系统TEC-CA/TEC-CA出厂光盘/实验/7-divider/db/divider_cmp.qrpt" Compiler "divider" "UNKNOWN" "V1" "E:/workroom/产品/开放式CPU实验教学系统TEC-CA/TEC-CA出厂光盘/实验/7-divider/db/divider.quartus_db" { Floorplan "E:/workroom/产品/开放式CPU实验教学系统TEC-CA/TEC-CA出厂光盘/实验/7-divider/" "" "1.900 ns" { clock remainder[6]~reg0 } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "1.900 ns" { clock clock~out remainder[6]~reg0 } { 0.000ns 0.000ns 1.400ns } { 0.000ns 0.500ns 0.000ns } } } } 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clock source 1.900 ns - Longest register " "Info: - Longest clock path from clock \"clock\" to source register is 1.900 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.500 ns) 0.500 ns clock 1 CLK PIN_79 18 " "Info: 1: + IC(0.000 ns) + CELL(0.500 ns) = 0.500 ns; Loc. = PIN_79; Fanout = 18; CLK Node = 'clock'" { } { { "E:/workroom/产品/开放式CPU实验教学系统TEC-CA/TEC-CA出厂光盘/实验/7-divider/db/divider_cmp.qrpt" "" { Report "E:/workroom/产品/开放式CPU实验教学系统TEC-CA/TEC-CA出厂光盘/实验/7-divider/db/divider_cmp.qrpt" Compiler "divider" "UNKNOWN" "V1" "E:/workroom/产品/开放式CPU实验教学系统TEC-CA/TEC-CA出厂光盘/实验/7-divider/db/divider.quartus_db" { Floorplan "E:/workroom/产品/开放式CPU实验教学系统TEC-CA/TEC-CA出厂光盘/实验/7-divider/" "" "" { clock } "NODE_NAME" } "" } } { "divider.vhd" "" { Text "E:/workroom/产品/开放式CPU实验教学系统TEC-CA/TEC-CA出厂光盘/实验/7-divider/divider.vhd" 10 -1 0 } } } 0} { "Info" "ITDB_NODE_DELAY" "IC(1.400 ns) + CELL(0.000 ns) 1.900 ns remainder\[7\]~reg0 2 REG LC1_J41 9 " "Info: 2: + IC(1.400 ns) + CELL(0.000 ns) = 1.900 ns; Loc. = LC1_J41; Fanout = 9; REG Node = 'remainder\[7\]~reg0'" { } { { "E:/workroom/产品/开放式CPU实验教学系统TEC-CA/TEC-CA出厂光盘/实验/7-divider/db/divider_cmp.qrpt" "" { Report "E:/workroom/产品/开放式CPU实验教学系统TEC-CA/TEC-CA出厂光盘/实验/7-divider/db/divider_cmp.qrpt" Compiler "divider" "UNKNOWN" "V1" "E:/workroom/产品/开放式CPU实验教学系统TEC-CA/TEC-CA出厂光盘/实验/7-divider/db/divider.quartus_db" { Floorplan "E:/workroom/产品/开放式CPU实验教学系统TEC-CA/TEC-CA出厂光盘/实验/7-divider/" "" "1.400 ns" { clock remainder[7]~reg0 } "NODE_NAME" } "" } } { "divider.vhd" "" { Text "E:/workroom/产品/开放式CPU实验教学系统TEC-CA/TEC-CA出厂光盘/实验/7-divider/divider.vhd" 64 -1 0 } } } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "0.500 ns 26.32 % " "Info: Total cell delay = 0.500 ns ( 26.32 % )" { } { } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.400 ns 73.68 % " "Info: Total interconnect delay = 1.400 ns ( 73.68 % )" { } { } 0} } { { "E:/workroom/产品/开放式CPU实验教学系统TEC-CA/TEC-CA出厂光盘/实验/7-divider/db/divider_cmp.qrpt" "" { Report "E:/workroom/产品/开放式CPU实验教学系统TEC-CA/TEC-CA出厂光盘/实验/7-divider/db/divider_cmp.qrpt" Compiler "divider" "UNKNOWN" "V1" "E:/workroom/产品/开放式CPU实验教学系统TEC-CA/TEC-CA出厂光盘/实验/7-divider/db/divider.quartus_db" { Floorplan "E:/workroom/产品/开放式CPU实验教学系统TEC-CA/TEC-CA出厂光盘/实验/7-divider/" "" "1.900 ns" { clock remainder[7]~reg0 } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "1.900 ns" { clock clock~out remainder[7]~reg0 } { 0.000ns 0.000ns 1.400ns } { 0.000ns 0.500ns 0.000ns } } } } 0} } { { "E:/workroom/产品/开放式CPU实验教学系统TEC-CA/TEC-CA出厂光盘/实验/7-divider/db/divider_cmp.qrpt" "" { Report "E:/workroom/产品/开放式CPU实验教学系统TEC-CA/TEC-CA出厂光盘/实验/7-divider/db/divider_cmp.qrpt" Compiler "divider" "UNKNOWN" "V1" "E:/workroom/产品/开放式CPU实验教学系统TEC-CA/TEC-CA出厂光盘/实验/7-divider/db/divider.quartus_db" { Floorplan "E:/workroom/产品/开放式CPU实验教学系统TEC-CA/TEC-CA出厂光盘/实验/7-divider/" "" "1.900 ns" { clock remainder[6]~reg0 } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "1.900 ns" { clock clock~out remainder[6]~reg0 } { 0.000ns 0.000ns 1.400ns } { 0.000ns 0.500ns 0.000ns } } } { "E:/workroom/产品/开放式CPU实验教学系统TEC-CA/TEC-CA出厂光盘/实验/7-divider/db/divider_cmp.qrpt" "" { Report "E:/workroom/产品/开放式CPU实验教学系统TEC-CA/TEC-CA出厂光盘/实验/7-divider/db/divider_cmp.qrpt" Compiler "divider" "UNKNOWN" "V1" "E:/workroom/产品/开放式CPU实验教学系统TEC-CA/TEC-CA出厂光盘/实验/7-divider/db/divider.quartus_db" { Floorplan "E:/workroom/产品/开放式CPU实验教学系统TEC-CA/TEC-CA出厂光盘/实验/7-divider/" "" "1.900 ns" { clock remainder[7]~reg0 } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "1.900 ns" { clock clock~out remainder[7]~reg0 } { 0.000ns 0.000ns 1.400ns } { 0.000ns 0.500ns 0.000ns } } } } 0} { "Info" "ITDB_FULL_TCO_DELAY" "1.100 ns + " "Info: + Micro clock to output delay of source is 1.100 ns" { } { { "divider.vhd" "" { Text "E:/workroom/产品/开放式CPU实验教学系统TEC-CA/TEC-CA出厂光盘/实验/7-divider/divider.vhd" 64 -1 0 } } } 0} { "Info" "ITDB_FULL_TSU_DELAY" "0.700 ns + " "Info: + Micro setup delay of destination is 0.700 ns" { } { { "divider.vhd" "" { Text "E:/workroom/产品/开放式CPU实验教学系统TEC-CA/TEC-CA出厂光盘/实验/7-divider/divider.vhd" 64 -1 0 } } } 0} } { { "E:/workroom/产品/开放式CPU实验教学系统TEC-CA/TEC-CA出厂光盘/实验/7-divider/db/divider_cmp.qrpt" "" { Report "E:/workroom/产品/开放式CPU实验教学系统TEC-CA/TEC-CA出厂光盘/实验/7-divider/db/divider_cmp.qrpt" Compiler "divider" "UNKNOWN" "V1" "E:/workroom/产品/开放式CPU实验教学系统TEC-CA/TEC-CA出厂光盘/实验/7-divider/db/divider.quartus_db" { Floorplan "E:/workroom/产品/开放式CPU实验教学系统TEC-CA/TEC-CA出厂光盘/实验/7-divider/" "" "11.600 ns" { remainder[7]~reg0 add_op~30 carries[0]~359 carries[1]~360 remainder~2126 remainder[6]~reg0 } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "11.600 ns" { remainder[7]~reg0 add_op~30 carries[0]~359 carries[1]~360 remainder~2126 remainder[6]~reg0 } { 0.000ns 1.100ns 0.200ns 1.100ns 0.200ns 0.200ns } { 0.000ns 2.000ns 1.700ns 1.900ns 2.200ns 1.000ns } } } { "E:/workroom/产品/开放式CPU实验教学系统TEC-CA/TEC-CA出厂光盘/实验/7-divider/db/divider_cmp.qrpt" "" { Report "E:/workroom/产品/开放式CPU实验教学系统TEC-CA/TEC-CA出厂光盘/实验/7-divider/db/divider_cmp.qrpt" Compiler "divider" "UNKNOWN" "V1" "E:/workroom/产品/开放式CPU实验教学系统TEC-CA/TEC-CA出厂光盘/实验/7-divider/db/divider.quartus_db" { Floorplan "E:/workroom/产品/开放式CPU实验教学系统TEC-CA/TEC-CA出厂光盘/实验/7-divider/" "" "1.900 ns" { clock remainder[6]~reg0 } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "1.900 ns" { clock clock~out remainder[6]~reg0 } { 0.000ns 0.000ns 1.400ns } { 0.000ns 0.500ns 0.000ns } } } { "E:/workroom/产品/开放式CPU实验教学系统TEC-CA/TEC-CA出厂光盘/实验/7-divider/db/divider_cmp.qrpt" "" { Report "E:/workroom/产品/开放式CPU实验教学系统TEC-CA/TEC-CA出厂光盘/实验/7-divider/db/divider_cmp.qrpt" Compiler "divider" "UNKNOWN" "V1" "E:/workroom/产品/开放式CPU实验教学系统TEC-CA/TEC-CA出厂光盘/实验/7-divider/db/divider.quartus_db" { Floorplan "E:/workroom/产品/开放式CPU实验教学系统TEC-CA/TEC-CA出厂光盘/实验/7-divider/" "" "1.900 ns" { clock remainder[7]~reg0 } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "1.900 ns" { clock clock~out remainder[7]~reg0 } { 0.000ns 0.000ns 1.400ns } { 0.000ns 0.500ns 0.000ns } } } } 0}
{ "Info" "ITDB_TSU_RESULT" "remainder\[3\]~reg0 dividend\[2\] clock 7.100 ns register " "Info: tsu for register \"remainder\[3\]~reg0\" (data pin = \"dividend\[2\]\", clock pin = \"clock\") is 7.100 ns" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "8.300 ns + Longest pin register " "Info: + Longest pin to register delay is 8.300 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(3.100 ns) 3.100 ns dividend\[2\] 1 PIN PIN_69 1 " "Info: 1: + IC(0.000 ns) + CELL(3.100 ns) = 3.100 ns; Loc. = PIN_69; Fanout = 1; PIN Node = 'dividend\[2\]'" { } { { "E:/workroom/产品/开放式CPU实验教学系统TEC-CA/TEC-CA出厂光盘/实验/7-divider/db/divider_cmp.qrpt" "" { Report "E:/workroom/产品/开放式CPU实验教学系统TEC-CA/TEC-CA出厂光盘/实验/7-divider/db/divider_cmp.qrpt" Compiler "divider" "UNKNOWN" "V1" "E:/workroom/产品/开放式CPU实验教学系统TEC-CA/TEC-CA出厂光盘/实验/7-divider/db/divider.quartus_db" { Floorplan "E:/workroom/产品/开放式CPU实验教学系统TEC-CA/TEC-CA出厂光盘/实验/7-divider/" "" "" { dividend[2] } "NODE_NAME" } "" } } { "divider.vhd" "" { Text "E:/workroom/产品/开放式CPU实验教学系统TEC-CA/TEC-CA出厂光盘/实验/7-divider/divider.vhd" 8 -1 0 } } } 0} { "Info" "ITDB_NODE_DELAY" "IC(3.900 ns) + CELL(1.300 ns) 8.300 ns remainder\[3\]~reg0 2 REG LC1_J39 4 " "Info: 2: + IC(3.900 ns) + CELL(1.300 ns) = 8.300 ns; Loc. = LC1_J39; Fanout = 4; REG Node = 'remainder\[3\]~reg0'" { } { { "E:/workroom/产品/开放式CPU实验教学系统TEC-CA/TEC-CA出厂光盘/实验/7-divider/db/divider_cmp.qrpt" "" { Report "E:/workroom/产品/开放式CPU实验教学系统TEC-CA/TEC-CA出厂光盘/实验/7-divider/db/divider_cmp.qrpt" Compiler "divider" "UNKNOWN" "V1" "E:/workroom/产品/开放式CPU实验教学系统TEC-CA/TEC-CA出厂光盘/实验/7-divider/db/divider.quartus_db" { Floorplan "E:/workroom/产品/开放式CPU实验教学系统TEC-CA/TEC-CA出厂光盘/实验/7-divider/" "" "5.200 ns" { dividend[2] remainder[3]~reg0 } "NODE_NAME" } "" } } { "divider.vhd" "" { Text "E:/workroom/产品/开放式CPU实验教学系统TEC-CA/TEC-CA出厂光盘/实验/7-divider/divider.vhd" 64 -1 0 } } } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "4.400 ns 53.01 % " "Info: Total cell delay = 4.400 ns ( 53.01 % )" { } { } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "3.900 ns 46.99 % " "Info: Total interconnect delay = 3.900 ns ( 46.99 % )" { } { } 0} } { { "E:/workroom/产品/开放式CPU实验教学系统TEC-CA/TEC-CA出厂光盘/实验/7-divider/db/divider_cmp.qrpt" "" { Report "E:/workroom/产品/开放式CPU实验教学系统TEC-CA/TEC-CA出厂光盘/实验/7-divider/db/divider_cmp.qrpt" Compiler "divider" "UNKNOWN" "V1" "E:/workroom/产品/开放式CPU实验教学系统TEC-CA/TEC-CA出厂光盘/实验/7-divider/db/divider.quartus_db" { Floorplan "E:/workroom/产品/开放式CPU实验教学系统TEC-CA/TEC-CA出厂光盘/实验/7-divider/" "" "8.300 ns" { dividend[2] remainder[3]~reg0 } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "8.300 ns" { dividend[2] dividend[2]~out remainder[3]~reg0 } { 0.000ns 0.000ns 3.900ns } { 0.000ns 3.100ns 1.300ns } } } } 0} { "Info" "ITDB_FULL_TSU_DELAY" "0.700 ns + " "Info: + Micro setup delay of destination is 0.700 ns" { } { { "divider.vhd" "" { Text "E:/workroom/产品/开放式CPU实验教学系统TEC-CA/TEC-CA出厂光盘/实验/7-divider/divider.vhd" 64 -1 0 } } } 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clock destination 1.900 ns - Shortest register " "Info: - Shortest clock path from clock \"clock\" to destination register is 1.900 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.500 ns) 0.500 ns clock 1 CLK PIN_79 18 " "Info: 1: + IC(0.000 ns) + CELL(0.500 ns) = 0.500 ns; Loc. = PIN_79; Fanout = 18; CLK Node = 'clock'" { } { { "E:/workroom/产品/开放式CPU实验教学系统TEC-CA/TEC-CA出厂光盘/实验/7-divider/db/divider_cmp.qrpt" "" { Report "E:/workroom/产品/开放式CPU实验教学系统TEC-CA/TEC-CA出厂光盘/实验/7-divider/db/divider_cmp.qrpt" Compiler "divider" "UNKNOWN" "V1" "E:/workroom/产品/开放式CPU实验教学系统TEC-CA/TEC-CA出厂光盘/实验/7-divider/db/divider.quartus_db" { Floorplan "E:/workroom/产品/开放式CPU实验教学系统TEC-CA/TEC-CA出厂光盘/实验/7-divider/" "" "" { clock } "NODE_NAME" } "" } } { "divider.vhd" "" { Text "E:/workroom/产品/开放式CPU实验教学系统TEC-CA/TEC-CA出厂光盘/实验/7-divider/divider.vhd" 10 -1 0 } } } 0} { "Info" "ITDB_NODE_DELAY" "IC(1.400 ns) + CELL(0.000 ns) 1.900 ns remainder\[3\]~reg0 2 REG LC1_J39 4 " "Info: 2: + IC(1.400 ns) + CELL(0.000 ns) = 1.900 ns; Loc. = LC1_J39; Fanout = 4; REG Node = 'remainder\[3\]~reg0'" { } { { "E:/workroom/产品/开放式CPU实验教学系统TEC-CA/TEC-CA出厂光盘/实验/7-divider/db/divider_cmp.qrpt" "" { Report "E:/workroom/产品/开放式CPU实验教学系统TEC-CA/TEC-CA出厂光盘/实验/7-divider/db/divider_cmp.qrpt" Compiler "divider" "UNKNOWN" "V1" "E:/workroom/产品/开放式CPU实验教学系统TEC-CA/TEC-CA出厂光盘/实验/7-divider/db/divider.quartus_db" { Floorplan "E:/workroom/产品/开放式CPU实验教学系统TEC-CA/TEC-CA出厂光盘/实验/7-divider/" "" "1.400 ns" { clock remainder[3]~reg0 } "NODE_NAME" } "" } } { "divider.vhd" "" { Text "E:/workroom/产品/开放式CPU实验教学系统TEC-CA/TEC-CA出厂光盘/实验/7-divider/divider.vhd" 64 -1 0 } } } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "0.500 ns 26.32 % " "Info: Total cell delay = 0.500 ns ( 26.32 % )" { } { } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.400 ns 73.68 % " "Info: Total interconnect delay = 1.400 ns ( 73.68 % )" { } { } 0} } { { "E:/workroom/产品/开放式CPU实验教学系统TEC-CA/TEC-CA出厂光盘/实验/7-divider/db/divider_cmp.qrpt" "" { Report "E:/workroom/产品/开放式CPU实验教学系统TEC-CA/TEC-CA出厂光盘/实验/7-divider/db/divider_cmp.qrpt" Compiler "divider" "UNKNOWN" "V1" "E:/workroom/产品/开放式CPU实验教学系统TEC-CA/TEC-CA出厂光盘/实验/7-divider/db/divider.quartus_db" { Floorplan "E:/workroom/产品/开放式CPU实验教学系统TEC-CA/TEC-CA出厂光盘/实验/7-divider/" "" "1.900 ns" { clock remainder[3]~reg0 } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "1.900 ns" { clock clock~out remainder[3]~reg0 } { 0.000ns 0.000ns 1.400ns } { 0.000ns 0.500ns 0.000ns } } } } 0} } { { "E:/workroom/产品/开放式CPU实验教学系统TEC-CA/TEC-CA出厂光盘/实验/7-divider/db/divider_cmp.qrpt" "" { Report "E:/workroom/产品/开放式CPU实验教学系统TEC-CA/TEC-CA出厂光盘/实验/7-divider/db/divider_cmp.qrpt" Compiler "divider" "UNKNOWN" "V1" "E:/workroom/产品/开放式CPU实验教学系统TEC-CA/TEC-CA出厂光盘/实验/7-divider/db/divider.quartus_db" { Floorplan "E:/workroom/产品/开放式CPU实验教学系统TEC-CA/TEC-CA出厂光盘/实验/7-divider/" "" "8.300 ns" { dividend[2] remainder[3]~reg0 } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "8.300 ns" { dividend[2] dividend[2]~out remainder[3]~reg0 } { 0.000ns 0.000ns 3.900ns } { 0.000ns 3.100ns 1.300ns } } } { "E:/workroom/产品/开放式CPU实验教学系统TEC-CA/TEC-CA出厂光盘/实验/7-divider/db/divider_cmp.qrpt" "" { Report "E:/workroom/产品/开放式CPU实验教学系统TEC-CA/TEC-CA出厂光盘/实验/7-divider/db/divider_cmp.qrpt" Compiler "divider" "UNKNOWN" "V1" "E:/workroom/产品/开放式CPU实验教学系统TEC-CA/TEC-CA出厂光盘/实验/7-divider/db/divider.quartus_db" { Floorplan "E:/workroom/产品/开放式CPU实验教学系统TEC-CA/TEC-CA出厂光盘/实验/7-divider/" "" "1.900 ns" { clock remainder[3]~reg0 } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "1.900 ns" { clock clock~out remainder[3]~reg0 } { 0.000ns 0.000ns 1.400ns } { 0.000ns 0.500ns 0.000ns } } } } 0}
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