divider.tan.summary

这个是用vhdl语言编写的除法器,仅仅供大家参考.

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Timing Analyzer Summary
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Type           : Worst-case tsu
Slack          : N/A
Required Time  : None
Actual Time    : 7.100 ns
From           : dividend[0]
To             : remainder[1]~reg0
From Clock     : 
To Clock       : clock
Failed Paths   : 0

Type           : Worst-case tco
Slack          : N/A
Required Time  : None
Actual Time    : 18.400 ns
From           : remainder[0]~reg0
To             : quotient[0]
From Clock     : clock
To Clock       : 
Failed Paths   : 0

Type           : Worst-case th
Slack          : N/A
Required Time  : None
Actual Time    : -4.900 ns
From           : dividend[3]
To             : remainder[4]~reg0
From Clock     : 
To Clock       : clock
Failed Paths   : 0

Type           : Worst-case Minimum tco
Slack          : N/A
Required Time  : None
Actual Time    : 12.400 ns
From           : remainder[8]~reg0
To             : remainder[8]
From Clock     : clock
To Clock       : 
Failed Paths   : 0

Type           : Clock Setup: 'clock'
Slack          : N/A
Required Time  : None
Actual Time    : 74.63 MHz ( period = 13.400 ns )
From           : remainder[7]~reg0
To             : remainder[6]~reg0
From Clock     : clock
To Clock       : clock
Failed Paths   : 0

Type           : Total number of failed paths
Slack          : 
Required Time  : 
Actual Time    : 
From           : 
To             : 
From Clock     : 
To Clock       : 
Failed Paths   : 0

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