usbn9603reg.h

嵌入式系统设计与开发实例详解－－基于ARM的应用（采用ARM7TDMI内核的、三星公司推出的S3C44B0X） 第六部分：ucos_ex2,ucos_ex3,UDPtest,USBN9603demo

/*----------------------------------------------------------------------------
 *  Copyright (c) 2001 by National Semiconductor Corporation
 *  National Semiconductor Corporation
 *  2900 Semiconductor Drive
 *  Santa Clara, California 95051
 *
 *  All rights reserved
 *
 *<<<-------------------------------------------------------------------------
 * File Contents:
 *	usbn9603reg.c - USBN9603 registers definitions
 *
 *  Project: USB Demo Application
 *  Author : Yan Nosovitsky
 *  Date   : Dec 2001
 *----------------------------------------------------------------------->>>*/
#ifndef __usb_reg_h__
#define __usb_reg_h__


typedef struct {
	char		name[10];
	BYTE		address;
	BYTE		type;
	BYTE		listIndex;
} USBN9603reg;
/*--------------------------------------------------------------------------*/
/*-----------------------   Configuration Registers   ----------------------*/
/*--------------------------------------------------------------------------*/

#define	NO_LIMIT		0x1
#define	READ_ONLY		0x2
#define WRITE_ONLY		0x4
#define	CLEARED_READ	0x8
#define CLEARED_WRITE	0x10
#define	NO_USE			0x20

USBN9603reg USBReg [] = { 
	{"MCNTRL",		0x00,	NO_LIMIT,	-1 },	                /*Main control register   */
	{"CCONF",		0x01,	NO_LIMIT,	-1 },					/*Clk. config. register   */
    {"NO",			0x02,	NO_USE,		-1 },					/* Reserved               */
	{"RID",			0x03,	READ_ONLY,	-1 },					/*Rev. ID      register   */  
	{"FAR",			0x04,	NO_LIMIT,	-1 },					/*Func address register   */  
	{"NFSR",		0x05,	NO_LIMIT,	-1 },					/*Node func st register   */   
	{"MAEV",		0x06,   READ_ONLY|CLEARED_READ,	-1 },		/*Main event   register   */  
	{"MAMSK",		0x07,	NO_LIMIT,	-1 },					/*Main mask    register   */  
	{"ALTEV",		0x08,   READ_ONLY|CLEARED_READ,	-1 },		/*Alt. event   register   */  
	{"ALTMSK",		0x09,	NO_LIMIT,	-1 },					/*ALT  mask    register   */  
	{"TXEV",		0x0A,	READ_ONLY,	-1 },					/*TX   event   register   */ 
	{"TXMSK",		0x0B,	NO_LIMIT,	-1 },		            /*TX   mask    register   */   
	{"RXEV",		0x0C,   READ_ONLY|CLEARED_READ,	-1 },		/*RX   event   register   */ 
	{"RXMSK",		0x0D,	NO_LIMIT,	-1 },					/*RX   mask    register   */   
	{"NAKEV",		0x0E,   READ_ONLY|CLEARED_READ,	-1 },		/*NAK  event   register   */  
	{"NAKMSK",		0x0F,	NO_LIMIT,	-1 },					/*NAK  mask    register   */  
	{"FWEV",		0x10,	READ_ONLY,	-1 },					/*FIFO warning register   */   
	{"FWMSK",		0x11,	NO_LIMIT,	-1 },					/*FIFO warning mask       */  
	{"FNH",			0x12,	READ_ONLY|WRITE_ONLY,	-1 },		/*Frame nbr hi register   */   
	{"FNL",			0x13,	READ_ONLY,	-1 },					/*Frame nbr lo register   */  
	{"DMACNTRL",	0x14,	NO_LIMIT,	-1 },					/*DMA  control register   */  
	{"DMAEV",		0x15,	READ_ONLY|CLEARED_WRITE,-1 },		/*DMA  event   register	  */
	{"DMAMSK",		0x16,	NO_LIMIT,	-1 },					/*DMA  mask	   register   */
	{"MIR",			0x17,	READ_ONLY,	-1 },					/*Mirror Register		  */
	{"DMACNT",		0x18,	NO_LIMIT,	-1 },				    /*DMA  count   register   */
	{"DMAERR",		0x19,	NO_LIMIT,	-1 },					/*DMA  error counnt register */ 
	{"NO",			0x1a,	NO_USE,		-1 },					/* Reserved				  */
	{"WKUP",		0x1b,	NO_LIMIT|CLEARED_WRITE,	-1 },		/*Wake-Up Register		  */
	{"NO",			0x1c,	NO_USE,		-1 },					/* Reserved				  */
	{"NO",			0x1d,	NO_USE,		-1 },					/* Reserved				  */
	{"NO",			0x1e,	NO_USE,		-1 },					/* Reserved				  */
	{"NO",			0x1f,	NO_USE,		-1 },					/* Reserved				  */
	{"EPC0",		0x20,   NO_LIMIT|READ_ONLY,		-1 },       /*Endpoint0    register   */   
	{"TXD0",		0x21,	NO_LIMIT ,	-1 },					/*TX   data    register 0 */  
	{"TXS0",		0x22,	READ_ONLY|CLEARED_READ,	-1 },		/*TX   status  register 0 */ 
	{"TXC0",		0x23,   NO_LIMIT,	-1 },		            /*TX   command register 0 */ 
	{"NO",			0x24,	NO_USE,		-1 },					/* Reserved				  */
	{"RXD0",		0x25,	NO_LIMIT,	-1 },					/*RX   data    register 0 */   
	{"RXS0",		0x26,	READ_ONLY|CLEARED_READ,	-1 },		/*RX   status  register 0 */   
	{"RXC0",		0x27,	NO_LIMIT,	-1 },					/*RX   command register 0 */    
	{"EPC1",		0x28,	NO_LIMIT,	-1 },					/*Endpoint1    register   */   
	{"TXD1",		0x29,   WRITE_ONLY,	-1 },					/*TX   data    register 1 */  
	{"TXS1",		0x2A,	READ_ONLY|CLEARED_READ,	-1 },		/*TX   status  register 1 */ 
	{"TXC1",		0x2B,	NO_LIMIT,	-1 },					/*TX   command register 1 */  
	{"EPC2",		0x2C,	NO_LIMIT,	-1 },					/*Endpoint2    register   */   
	{"RXD1",		0x2D,	READ_ONLY,	-1 },					/*RX   data    register 1 */   
	{"RXS1",		0x2E,	READ_ONLY|CLEARED_READ,	-1 },		/*RX   status  register 1 */   
	{"RXC1",		0x2F,	NO_LIMIT,	-1 },					/*RX   command register 1 */   
 	{"EPC3",		0x30,	NO_LIMIT,	-1 },					/*Endpoint3    register   */   
	{"TXD2",		0x31,   WRITE_ONLY,	-1 },					/*TX   data    register 2 */  
	{"TXS2",		0x32,	READ_ONLY|CLEARED_READ,	-1 },		/*TX   status  register 2 */ 
	{"TXC2",		0x33,	NO_LIMIT,	-1 },					/*TX   command register 2 */  	 
	{"EPC4",		0x34,	NO_LIMIT,	-1 },					/*Endpoint4    register   */   
	{"RXD2",		0x35,	READ_ONLY,	-1 },					/*RX   data    register 2 */   
	{"RXS2",		0x36,	READ_ONLY|CLEARED_READ,	-1 },		/*RX   status  register 2 */   
	{"RXC2",		0x37,	NO_LIMIT,	-1 },					/*RX   command register 2 */   
	{"EPC5",		0x38,	NO_LIMIT,	-1 },					/*Endpoint5    register   */   
	{"TXD3",		0x39,   WRITE_ONLY,	-1 },					/*TX   data    register 3 */  
	{"TXS3",		0x3A,	READ_ONLY|CLEARED_READ,	-1 },		/*TX   status  register 3 */ 
	{"TXC3",		0x3B,	NO_LIMIT,	-1 },					/*TX   command register 3 */   
	{"EPC6",		0x3C,	NO_LIMIT,	-1 },					/*Endpoint6    register   */   
	{"RXD3",		0x3D,	READ_ONLY,	-1 },					/*RX   data    register 3 */   
	{"RXS3",		0x3E,	READ_ONLY|CLEARED_READ,	-1 },		/*RX   status  register 3 */   
	{"RXC3",		0x3F,	NO_LIMIT,	-1 },					/*RX   command register 3 */   
	 };

#define LAST_REG	0x3f
#endif __usb_reg_h__