atmtxbyte.c

摩托罗拉Motolola公司网络处理器C3的示范代码.实现了ATM的AAL2层交换功能.想了解网络处理器的可以

    Bbus(Payload);
    ALU(PassB);
    Actions(UnloadFIFO + IregsAwrite);
    Branch(ALWAYS, Label(GIVE_MERGE_TO_RC));      /* clock 2 */

#endif

    /*
     *  AAL5 CPCS PDU Payload Processing - This payload is an AAL5 CPCS PDU,
     *    send multiple cells using the same header.  This code assumes that
     *    the payload is at least 2 cells long.
     *
     *  Note: when control reaches this point, the header for
     *  the first cell of the AAL5 PDU has already been sent.
     *  The payload of all but the last cell should not have merge9 on the last byte.
     */
LabelDef(AAL5_CPCS_PDU_PAYLOAD_PROCESS);

#define HdrByte0 Ireg4
#define HdrByte1 Ireg5
#define HdrByte2 Ireg6
#define HdrByte3 Ireg7

    Actions(CregAddrIncr);      /* Advance Creg Address to cellHeader[1] */
    Branch(ALWAYS, Upc+1);

    DCPSIM_MESSAGE(MERGE_HDR_BYTE0);
    CregToIreg(HdrByte0);       /* HdrByte0 = [GFC/VPI<11:8>, VPI<7:4>] */
    Actions(CregAddrIncr);      /* Advance Creg Address to cellHeader[2] */
    Branch(ALWAYS, Upc+1);

    DCPSIM_MESSAGE(MERGE_HDR_BYTE1);
    CregToIreg(HdrByte1);       /* HdrByte1 = [VPI<3:0>, VCI<15:12>] */
    Actions(CregAddrIncr);      /* Advance Creg Address to cellHeader[3] */
    Branch(ALWAYS, Upc+1);

    DCPSIM_MESSAGE(MERGE_HDR_BYTE2);
    CregToIreg(HdrByte2);       /* HdrByte2 = [VCI<11:4>] */
    Actions(CregAddrIncr);      /* Advance Creg Address to payloadLength[0] */
    Branch(ALWAYS, Upc+1);

    DCPSIM_MESSAGE(MERGE_HDR_BYTE3);
    CregToIreg(HdrByte3);       /* HdrByte3 = [VCI<3:0>, <PTI, CLP>] */
    Actions(CregAddrIncr);      /* Advance Creg Address to payloadLength[1] */
    Branch(ALWAYS, Upc+1);

#define PayloadLengthMsb Ireg2
#define PayloadLengthLsb Ireg3

    DCPSIM_MESSAGE(MERGE_PAYLOAD_LENGTH_MSB);
    CregToIreg(PayloadLengthMsb);   /* Payload Length MSB */
    Branch(ALWAYS, Upc+1);

    DCPSIM_MESSAGE(MERGE_PAYLOAD_LENGTH_LSB);
    CregToIreg(PayloadLengthLsb);   /* Payload Length LSB */
    CregsAddrWrite(TXSTATUS);       /* Reset Creg Address to TxStatus */
    Branch(ALWAYS, Upc+1);

    Branch(ALWAYS, Upc+1);

    Branch(AllOnes(PayloadLengthLsb), Label(TRANSMIT_AAL5_EOM_CELL_HEADER));

LabelDef(TRANSMIT_AAL5_CELL_HEADER);

    DCPSIM_MESSAGE(TRANSMIT_AAL5_CELL_HEADER);
    Actions(HECinit);               /* Initialize the HEC */
    IregANDlit(STATUSreg, ~SCRAM);  /* Turn off Cell Payload Scrambling during header */
    Branch(ALWAYS, Upc+1);

    IregXmit(HdrByte0);
    Branch(ALWAYS, Upc+1);      /* HdrByte0 Sent */

    IregXmit(HdrByte1);
    Branch(ALWAYS, Upc+1);      /* HdrByte1 Sent */

    IregXmit(HdrByte2);
    Branch(ALWAYS, Upc+1);      /* HdrByte2 Sent */

    IregXmit(HdrByte3);
    Branch(ALWAYS, Upc+1);      /* HdrByte3 Sent */

    IregInit(CellByteCnt, -ATM_CELL_PAYLD_SZ, UseAbus);
    Branch(ALWAYS, Upc+1);      /* Delay slot to let HEC setup. */

    Bbus(HEC);
    Abus(Literal(HEC_COSET));
    ALU(XOR);
    PayloadOut(ALUout);
    Branch(ALWAYS, Upc+1);

LabelDef(TRANSMIT_AAL5_CELL_PAYLOAD);

    DCPSIM_MESSAGE(TRANSMIT_AAL5_CELL_PAYLOAD);
    IregORlit(STATUSreg, SCRAM);    /* Turn on Cell Payload Scrambling, */
    Branch(ALWAYS, Upc+1);          /* RC will override off via a mode reg bit */

    Actions(IregIncr(CellByteCnt) + IregIncr(PayloadLengthLsb) + UnloadFIFO + RepeatUntil);
    PayloadOut(Payload);
    Branch(AllOnes(CellByteCnt), Upc+1); /* Transmit bytes to TxFifo */

    BranchNot(AllOnes(PayloadLengthLsb), Label(TRANSMIT_AAL5_CELL_HEADER));

#undef PayloadLengthMsb
#undef PayloadLengthLsb

LabelDef(TRANSMIT_AAL5_EOM_CELL_HEADER);

    DCPSIM_MESSAGE(TRANSMIT_AAL5_EOM_CELL_HEADER);
    Actions(HECinit);               /* Initialize the HEC */
    IregANDlit(STATUSreg, ~SCRAM);  /* Turn off Cell Payload Scrambling during header */
    Branch(ALWAYS, Upc+1);

    IregORlit(HdrByte3, Aal5EomBit);    /* set the EOM bit in the last cell */
    Branch(ALWAYS, Upc+1);

    IregXmit(HdrByte0);
    Branch(ALWAYS, Upc+1);      /* HdrByte0 Sent */

    IregXmit(HdrByte1);
    Branch(ALWAYS, Upc+1);      /* HdrByte1 Sent */

    IregXmit(HdrByte2);
    Branch(ALWAYS, Upc+1);      /* HdrByte2 Sent */

    IregXmit(HdrByte3);
    Branch(ALWAYS, Upc+1);      /* HdrByte3 Sent */

#undef HdrByte0
#undef HdrByte1
#undef HdrByte2
#undef HdrByte3

    IregInit(CellByteCnt, -(ATM_CELL_PAYLD_SZ-1), UseAbus);
    Branch(ALWAYS, Upc+1);      /* Delay slot to let HEC setup. */

    Bbus(HEC);
    Abus(Literal(HEC_COSET)); /* Add CoSet to 4 byte HEC */
    ALU(XOR);
    PayloadOut(ALUout);
    Branch(ALWAYS, Upc+1);

LabelDef(TRANSMIT_AAL5_EOM_CELL_PAYLOAD);

    DCPSIM_MESSAGE(TRANSMIT_AAL5_EOM_CELL_PAYLOAD);
    IregORlit(STATUSreg, SCRAM);    /* Turn on Cell Payload Scrambling, */
    Branch(ALWAYS, Upc+1);          /* RC will override off via a mode reg bit */

    /*
     * Send the cell - less the last byte
     */
    PayloadOut(Payload);
    Actions(IregIncr(CellByteCnt) + UnloadFIFO + RepeatUntil);
    Branch(AllOnes(CellByteCnt), Upc+1); /* Transmit bytes to TxFifo */

    PayloadOut(Payload);
    Actions(UnloadFIFO + Merge9);
    Branch(ALWAYS, Label(GIVE_MERGE_TO_RC));

    /*
     *  OAM Cell Processing - This cell is an OAM cell,
     *    insert the 10-bit CRC in the last two bytes
     */
LabelDef(OAM_CELL_PAYLOAD_PROCESS);

    DCPSIM_MESSAGE(OAM_CELL_PAYLOAD_PROCESS);
    Abus(Creg);
    ALU(PassA);
    Pbus(ALUout);
    Actions(DataOutValid+CregAddrIncr);
    Branch(ALWAYS, Upc+1);                        /* clock 0 */
    Branch(ALWAYS, Upc+1);                        /* clock 1 */

    Abus(Creg);
    ALU(PassA);
    Pbus(ALUout);
    Actions(DataOutValid+CregAddrIncr);
    Branch(ALWAYS, Upc+1);                        /* clock 0 */
    Branch(ALWAYS, Upc+1);                        /* clock 1 */

    Abus(Creg);
    ALU(PassA);
    Pbus(ALUout);
    Actions(DataOutValid+CregAddrIncr);
    Branch(ALWAYS, Upc+1);                        /* clock 0 */
    Branch(ALWAYS, Upc+1);                        /* clock 1 */

    CregsAddrWrite(TXSTATUS);
    Abus(Creg);
    ALU(PassA);
    Pbus(ALUout);
    Actions(DataOutValid);
    Branch(ALWAYS, Upc+1);                        /* clock 0 */

    DCPSIM_MESSAGE(TRANSMIT_HEC);

#if DCP_CHIP_REV >= DCP_C5_D0
    IregInit(CellByteCnt, -ATM_CELL_PAYLD_SZ+2, UseAbus);
    Branch(ALWAYS, Upc+1);
#else
    IregInit(CellByteCnt, -ATM_CELL_PAYLD_SZ+3, UseAbus);
    Branch(ALWAYS, Upc+1);                        /* clock 1 */
#endif

    DCPSIM_MESSAGE(TRANSMIT_OAM_PAYLOAD);
    Bbus(HEC);
    Abus(Literal(HEC_COSET));
    ALU(XOR);
    PayloadOut(ALUout);
    Branch(ALWAYS, Upc+1);                        /* clock 0 */

    IregORlit(STATUSreg, SCRAM);
    Actions(CRC10init);
    Branch(ALWAYS, Upc+1);                        /* clock 1 */

    Branch(ALWAYS, Upc+1);                        /* clock 2 */

    Pbus(Payload);
    Actions(UnloadFIFO+CRC10accum+DataOutValid+IregIncr(CellByteCnt) + RepeatUntil);
    Branch(AllOnes(CellByteCnt), Upc+1);          /* clock 0 */

#if DCP_CHIP_REV < DCP_C5_D0
    /* save second from last byte to send later */
    IregsA(LastByteMinus2);
    Bbus(Payload);
    ALU(PassB);
    Actions(UnloadFIFO + IregsAwrite + CRC10accum);
    Branch(ALWAYS, Upc+1);                        /* clock 1 */
#endif

    Branch(ALWAYS, Upc+1);                        /* clock 2 */

    /***************************************************************************
     *  Send the 47th and 48th bytes:
     *    47th byte: upper 6 bits of payload or'ed with the upper 2 bits of CRC
     *    48th byte: lower 8 bits of CRC
     *
     *  The timing on the following sequence is tricky, here it is:
     *
     * Cycle  Settings                  Effect
     * =====  ========                  ======
     *
     * N      Pbus=FIFOout
     *        Crc10AccumPartial         Puts 6 payload bits into the CRCaccum
     *
     * N+1    CRCctl=0 + CRC10readHigh  Sets up the CRC read of the top 2 bits
     *                                  of CRC10 Meanwhile, CRC accum working on
     *                                  6 bits
     *
     * M+2    Bbus(CRC)                 Selects lower 2 bits of CRC10 from the
     *                                  CRC read reg onto the Bbus.   Leave
     *                                  CRC10readHigh on during this operation
     *                                  No DavaOutValid or UnloadFIFO can occur
     *                                  on this cycle.
     *
     * N+3    CRCctl=0 + CRC10readLow   Sets up the CRC read of the lower 8 bits
     *                                  of CRC10
     *
     * N+4    Bbus(CRC)                 Selects upper 8 bits of CRC10 from the
     *                                  CRC read reg onto the Bbus.
     ***************************************************************************
     */

    DCPSIM_MESSAGE(TRANSMIT_OAM_CRC10);

    /* Cycle N - Capture the 47th byte from DMEM in Ireg1 */
    Abus(Payload);
    ALU(PassA);
    IregsA(Ireg1);
    Actions(CRC10accumPartial+UnloadFIFO+IregsAwrite);
    Branch(ALWAYS, Upc+1);                        /* clock 3 */

    /* Cycle N+1 - Setup read of top 2 bits of CRC10
     *           - Clear the lower 2 bits of the 47th payload byte
     */
    Abus(IregsA(Ireg1));
    Bbus(Literal(0xFC));
    ALU(AND);
    Actions(IregsAwrite + CRC10readHigh);
    Branch(ALWAYS, Upc+1);                        /* clock 4 */

    /* Cycle N+2 - read CRC10 and save */
    IregsA(Ireg2);
    ALU(PassB);
    Bbus(CRC10);
    Actions(CRC10readHigh + IregsAwrite);
    Branch(ALWAYS, Upc+1);                        /* clock 5 */

#if DCP_CHIP_REV >= DCP_C5_D0
    /*
     * Cycle N+3 - read low, and send out 47th
     * byte out (OR CRC10 high with upper 6 bits)
     */
    Abus(IregsA(Ireg1));
    Bbus(IregsB(Ireg2));
    ALU(OR);
    PayloadOut(ALUout);
    Actions(CRC10readLow);
    Branch(ALWAYS, Upc+1);

    /*
     * Cycle N+4 - Send the 48th byte out
     * discard the 48th byte of payload from DMEM
     * send the lower 8 bits of CRC10 in its place
     */
    Actions(UnloadFIFO);
    Bbus(CRC10);
    ALU(PassB);
    PayloadOut(ALUout);
    Actions(Merge9);
    Branch(ALWAYS, Label(GIVE_MERGE_TO_RC));
#else
    /* Cycle N+3 - read low, and save 47th byte (OR CRC10 high with upper 6 bits) */
    Abus(IregsA(Ireg1));
    Bbus(IregsB(Ireg2));
    ALU(OR);
    Actions(CRC10readLow + IregsAwrite);
    Branch(ALWAYS, Upc+1);                        /* clock 6 */

    /* Cycle N+4 - save the 48th byte */
    /* discard the 48th byte of payload from DMEM */
    IregsA(LastByte);
    Bbus(CRC10);
    ALU(PassB);
    Actions(UnloadFIFO + IregsAwrite);
    Branch(ALWAYS, Upc+1);                        /* clock 7 */

    Abus(IregsA(LastByteMinus2));
    ALU(PassA);
    Pbus(ALUout);
    Actions(DataOutValid);
    Branch(ALWAYS, Upc+1);                        /* clock 0 */

    IregsA(LastByteMinus1);
    Bbus(IregsB(Ireg1));
    ALU(PassB);
    Actions(IregsAwrite);
    Branch(ALWAYS, Label(GIVE_MERGE_TO_RC));      /* clock 1 */
#endif
}