aal2txtxbyte.c

摩托罗拉Motolola公司网络处理器C3的示范代码.实现了ATM的AAL2层交换功能.想了解网络处理器的可以

/*****************************************************************************
* Copyright (c) 1998, 1999, 2000, 2001, 2002 C-Port Corporation, a Motorola Company
* All Rights Reserved
*
* The information contained in this file is C-Port Corporation confidential
* and proprietary. Any reproduction, use or disclosure, in whole or in part,
* of this program, including any attempt to obtain a human-readable version
* of this program, without the express, prior written consent of C-Port
* Corporation or Motorola Incorporated is strictly prohibited.
 *****************************************************************************/
/*****************************************************************************
 * TxByte Functionality for AAL2Tx Module, as described in AAL2 Tx Design
 * Document.
 *****************************************************************************/
#define TXBYTE
/*---------------------------------------------------------------------------*/
#include <sdpUcode.h>
#include <dcpRegistersCp.h>
#include <rcSdpAal2TxApiIf.h>
#include <rcSdpAal2RxApiIf.h>
#include <stdio.h>

/*---------------------------------------------------------------------------*/
/*---------------------------------------------------------------------------*/
/*---------------------------------------------------------------------------*/
/*****************************************************************************
 * TxByte Functionality for AAL2Tx Module, as described in AAL2 Tx Design
 * Document.
 *****************************************************************************/
/*---------------------------------------------------------------------------*/
#define MERGE                   ((int) &((SdpTxCregs*)NULL)->merge)
#define TXSTATUS                ((int) &((SdpTxCregs*)NULL)->txStatus)

#define AAL2TXMERGE             (MERGE + (int) &((MergeSpc*)NULL)->Aal2TxMergeSpc)
#define RC_OWN_FLG              (TXSTATUS_OWN >> 8)
#define CPS_PH_SIZE             3

#define IREG_TEMP_STORAGE_1                                     Ireg0
#define IREG_TEMP_STORAGE_2                                     Ireg1
#define IREG_RETURN_ADDRESS                                     Ireg2
#define IREG_CPS_PAYLOAD_COUNT                          Ireg3
#define IREG_PREV_SDU_RECIRC_BYTES_COUNT        Ireg4
#define IREG_STF_1                                                      Ireg5
#define IREG_STF_1_POSITION                                     Ireg6
#define IREG_CID                                                        Ireg7
#define IREG_CPS_PH_2ND_BYTE                            Ireg8
#define IREG_CPS_PH_3RD_BYTE                            Ireg9
/*---------------------------------------------------------------------------*/
void TxCidAccumCrc5 (int EofFlag);
void TxCpsPh2ndByteAccumCrc5 (int EofFlag);
void PrepareTxCpsPh3rdByte (int EofFlag);
/*---------------------------------------------------------------------------*/
void
SDPmain()
{
        Description = ("AAL2 Tx Microcode for the SDP TxByte Processor.");
/*---------------------------------------------------------------------------*/
/* Polling for the merge space to become available for the TxByte processor */
LabelDef(LOAD_TX_STATUS_ADDR);

    /*DCPSIM_MESSAGE(LOAD_TX_STATUS_ADDR);*/

        CregsAddrWrite(TXSTATUS);
    Branch(ALWAYS, Upc+1);
    Branch(ALWAYS, Upc+1);
/*---------------------------------------------------------------------------*/
LabelDef(CHECK_MERGE_OWNERSHIP);
    /*DCPSIM_MESSAGE(CHECK_MERGE_OWNERSHIP);*/

    Abus(Creg);
    Bbus(Literal(RC_OWN_FLG));
    ALU(AND);
    Branch(ALWAYS, Upc+1);

    Branch(ALUzero, Label(POLL_FOR_CPS_PAYLOAD));
    Branch(ALWAYS, Label(CHECK_MERGE_OWNERSHIP));
/*---------------------------------------------------------------------------*/
/* Handover merge space to RC */
LabelDef(GIVE_MERGE_TO_RC);

    DCPSIM_MESSAGE(GIVE_MERGE_TO_RC);

        /* Creg contains the address of TxStatus */
    CregsAddrWrite(TXSTATUS);
    Branch(ALWAYS, Upc+1);
    Branch(ALWAYS, Upc+1);

    Abus(Creg);
    Bbus(Literal(RC_OWN_FLG));
    ALU(OR);
    Pbus(ALUout);
    Actions(CregsWrite);
    Branch(ALWAYS, Upc+1);

    Branch(ALWAYS, Label(LOAD_TX_STATUS_ADDR));
/*---------------------------------------------------------------------------*/
LabelDef(POLL_FOR_CPS_PAYLOAD);

        /*DCPSIM_MESSAGE(POLL_FOR_CPS_PAYLOAD);*/
    Actions(RepeatUntil);
    Branch(RxDataValid, Upc+1);
/*---------------------------------------------------------------------------*/
/* Merge space is owned by the TxByte processor, read it */
LabelDef(READ_MERGE_SPACE);

    DCPSIM_MESSAGE(READ_MERGE_SPACE);

        /* Init CRC-5 accumulation */
        Actions(CRC5init);
        Branch(ALWAYS, Upc+1);

        /* Save the microaddress for return */
        CopyIreg(IREG_RETURN_ADDRESS,PCreg);
        /* Branch for forming and storing CPS packet header 1st, 2nd and partial 3rd
         * bytes in Iregs. Does not caclculate HEC(CRC-5) here, 3rd byte contains
         * partial uui.
         */
        Branch(ALWAYS, Label(FORM_CPS_PH_1ST_2ND_AND_PARTIAL_3RD_BYTES));

        /* Save STF-1 position in Ireg */
    CregsAddrWrite(AAL2TXMERGE + (int) &((Aal2TxMergeSpace*)NULL)->PositionStf1);
    Branch(ALWAYS, Upc+1);
    Branch(ALWAYS, Upc+1);

        CregToIreg(IREG_STF_1_POSITION);
        Branch(ALWAYS, Upc+1);

        /* Store Prev ATM SDU recirculation bytes count in an Ireg */
        CregsAddrWrite(AAL2TXMERGE + (int) &((Aal2TxMergeSpace*)NULL)->CountAtmBytesRecir);
    Branch(ALWAYS, Upc+1);
    Branch(ALWAYS, Upc+1);

        CregToIreg (IREG_PREV_SDU_RECIRC_BYTES_COUNT);
        Branch(ALWAYS, Upc+1);

        /* Check the first STF byte */
    CregsAddrWrite(AAL2TXMERGE + (int) &((Aal2TxMergeSpace*)NULL)->Stf1);
    Branch(ALWAYS, Upc+1);
    Branch(ALWAYS, Upc+1);

        /* Save STF-1 in IREG_STF_1 Ireg */
        CregToIreg(IREG_STF_1);
        Branch(ALWAYS, Upc+1);

        /* Check STF-1 value */
    Abus(Creg);
    ALU(PassA);
        Branch(ALWAYS, Upc+1);
    Branch(ALUzero, Label(NO_STF_PRESENT));

        /* There is one STF Byte, check the second STF byte */
    CregsAddrWrite(AAL2TXMERGE + (int) &((Aal2TxMergeSpace*)NULL)->Stf2);
    Branch(ALWAYS, Upc+1);
    Branch(ALWAYS, Upc+1);
    Abus(Creg);
    ALU(PassA);

        Branch(ALWAYS, Upc+1);
    Branch(ALUzero, Label(NO_SECOND_STF_PRESENT));
/*----------------------------------------------------------------------------*/
/* Process when two STF bytes are present in the merge space */
LabelDef(TWO_STF_PRESENT);

    DCPSIM_MESSAGE(TWO_STF_PRESENT);

        /* Check if previous ATM SDU bytes are being recirculated because of
         * non-alignment issue.
         */
        Abus(IregsA(IREG_PREV_SDU_RECIRC_BYTES_COUNT));
        ALU(PassA);
        Branch(ALWAYS, Upc+1);
    Branch(ALUzero, Label(INSERT_TWO_STF));

        /* Previous ATM SDU bytes are non-zero, first transmit them */
        /* Save the microaddress for return */
        CopyIreg(IREG_RETURN_ADDRESS, PCreg);
        /* Branch for transmitting prev ATM SDU  */
        Branch(ALWAYS, Label(TX_PREV_ATM_SDU));
/*---------------------------------------------------------------------------*/
/* Now insert STFs */
LabelDef(INSERT_TWO_STF);

    DCPSIM_MESSAGE(INSERT_TWO_STF);

        /* Check the content */
        Abus(IregsA(IREG_STF_1_POSITION));
    ALU(PassA);
        Branch(ALWAYS, Upc+1);
        /* Position for STF-1 is zero, it means two new ATM SDUs will be formed */
    Branch(ALUzero, Label(TWO_NEW_ATM_SDU));

        /* Otherwise, subtract CPS-PH size from STF position */
        CopyIreg(IREG_TEMP_STORAGE_1, IREG_STF_1_POSITION);
        Branch(ALWAYS, Upc+1);

        IregSUBlit(IREG_TEMP_STORAGE_1, CPS_PH_SIZE);
        Branch(ALWAYS, Upc+1);

        Abus(IregsA(IREG_TEMP_STORAGE_1));
        ALU(PassA);
        Branch(ALWAYS, Upc+1);
        Branch(ALUneg, Label(TWO_STF_INSERT_STF_1_IN_BETW_CPS_PH));
        Branch(ALUzero, Label(TWO_STF_INSERT_STF_1_IMM_AFTER_CPS_PH));
        Branch(ALWAYS, Label(TWO_STF_INSERT_STF_1_IN_CPS_PAYLOAD));
/*---------------------------------------------------------------------------*/
/* 1 or 2 bytes of the CPS-PH fills the previous ATM SDU, rest of the bytes come
 * in the next SDU.
 */
LabelDef(TWO_STF_INSERT_STF_1_IN_BETW_CPS_PH);

    DCPSIM_MESSAGE(TWO_STF_INSERT_STF_1_IN_BETW_CPS_PH);

        /* Store STF-1 position */
        CopyIreg(IREG_TEMP_STORAGE_1, IREG_STF_1_POSITION);
        Branch(ALWAYS, Upc+1);

        /* Subtract  CPS_PH_SIZE - 2 to find out the location of STF insertion,
         * within CPS-PH.
         */
        IregSUBlit(IREG_TEMP_STORAGE_1, CPS_PH_SIZE - 2);
        Branch(ALWAYS, Upc+1);

        Abus(IregsA(IREG_TEMP_STORAGE_1));
        ALU(PassA);
        Branch(ALWAYS, Upc+1);
        Branch(ALUzero, Label(INSERT_STF1_AFTER_CID));

        /* Transmit IREG_CID: CPS-PH 1st Byte */
        TxCidAccumCrc5 (FALSE);
        Branch(ALWAYS, Upc+1);

        /* Transmit CPS-PH 2nd byte with EOF */
        TxCpsPh2ndByteAccumCrc5 (TRUE);
        Branch(ALWAYS, Upc+1);

        /* Transmit STF */
        IregXmit(IREG_STF_1);
        Branch(ALWAYS, Upc+1);

        IregInit(IREG_CPS_PAYLOAD_COUNT, -(46-1), UseBbus);
        Branch(ALWAYS, Upc+1);

        Branch(ALWAYS, Label(TX_UUI_AND_ONWARDS));
/*---------------------------------------------------------------------------*/
LabelDef(INSERT_STF1_AFTER_CID);
        DCPSIM_MESSAGE(INSERT_STF1_AFTER_CID);

        /* Transmit IREG_CID with EOF */
        TxCidAccumCrc5 (TRUE);
        Branch(ALWAYS, Upc+1);

        /* Transmit STF 1 */
        IregXmit(IREG_STF_1);
        Branch(ALWAYS, Upc+1);

        /* Transmit CPS-PH second Byte */
        TxCpsPh2ndByteAccumCrc5 (FALSE);
        Branch(ALWAYS, Upc+1);

        /* Load CPS Payload count */
        IregInit(IREG_CPS_PAYLOAD_COUNT, -(45-1), UseBbus);
        Branch(ALWAYS, Upc+1);
/*---------------------------------------------------------------------------*/
LabelDef(TX_UUI_AND_ONWARDS);
        DCPSIM_MESSAGE(TX_UUI_AND_ONWARDS);

        /* Transmit CPS-PH 3rd Byte */
        PrepareTxCpsPh3rdByte (FALSE);
        Branch(ALWAYS, Upc+1);

        /* Initialize IREG_TEMP_STORAGE_1 with a 0. It will count number
         * of payload bytes transmitted.
         */
        IregInit(IREG_TEMP_STORAGE_1, 0, UseBbus);
        Branch(ALWAYS, Upc+1);

        Branch(ALWAYS, Label(TX_CPS_PAYLOAD_ACROSS_TWO_SDU));
/*---------------------------------------------------------------------------*/
LabelDef(TWO_STF_INSERT_STF_1_IMM_AFTER_CPS_PH);
        DCPSIM_MESSAGE(TWO_STF_INSERT_STF_1_IMM_AFTER_CPS_PH);

        IregInit(IREG_CPS_PAYLOAD_COUNT, -(47-1), UseBbus);
        Branch(ALWAYS, Upc+1);

        Abus(AddressOf(Label(TX_CPS_PAYLOAD_ACROSS_TWO_SDU)));
        ALU(PassA);
        IregsA(IREG_RETURN_ADDRESS);
        Actions(IregsAwrite);
        Branch(ALWAYS,Upc+1);

        /* Subtract 1 from IREG_RETURN_ADDRESS, because it is getting
         * incrmented in INSERT_STF_IMM_AFTER_CPS_PH.
         */
        IregSUBlit(IREG_RETURN_ADDRESS, 1);
        Branch(ALWAYS, Upc+1);

        Branch(ALWAYS,Label(INSERT_STF_IMM_AFTER_CPS_PH));

        /* Initialize IREG_TEMP_STORAGE_1 with a 0. It will count number
         * of payload bytes transmitted.
         */
        IregInit(IREG_TEMP_STORAGE_1, 0, UseBbus);
        Branch(ALWAYS, Upc+1);

        /* Now execution control goes to TX_CPS_PAYLOAD_ACROSS_TWO_SDU */
/*---------------------------------------------------------------------------*/
LabelDef(TWO_STF_INSERT_STF_1_IN_CPS_PAYLOAD);
        DCPSIM_MESSAGE(TWO_STF_INSERT_STF_1_IN_CPS_PAYLOAD);

        /* Save the microaddress for return */
        CopyIreg(IREG_RETURN_ADDRESS,PCreg);
        /* Branch for Tx CPS-PH */
        Branch(ALWAYS, Label(TX_CPS_HEADER));

        CopyIreg(IREG_TEMP_STORAGE_1, IREG_STF_1_POSITION);
        Branch(ALWAYS, Upc+1);
       
        /*
         * Resolution for Bug 03236 : sub-bug Aal2 Tx CP Stalls
         * If stf has to be transmitted after 3 bytes of CPS 
         * header and one byte of payload, transmit one byte of payload
         * by branching to TRANMSIT_FIRST_PAYLOAD_BYTE, 
         * Tranmsit First Payload byte and then return to Label 
         * TRANMSIT_FIRST_STF to transmit the first STF.
         */
 
        IregSUBlit(IREG_TEMP_STORAGE_1, CPS_PH_SIZE+1);
        Branch(ALWAYS, Upc+1);

        IregTest(IREG_TEMP_STORAGE_1,UseAbus);
        Branch(ALWAYS,Upc+1);
        Branch(ALUzero, Label(TRANSMIT_FIRST_PAYLOAD_BYTE));

        /* Initialize IREG_CPS_PAYLOAD_COUNT with a 0 */
        IregInit(IREG_CPS_PAYLOAD_COUNT, 0, UseBbus);
        Branch(ALWAYS, Upc+1);

        /* Make IREG_CPS_PAYLOAD_COUNT negative */
        IregSUB(IREG_CPS_PAYLOAD_COUNT, IREG_TEMP_STORAGE_1);
        Branch(ALWAYS, Upc+1);