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📄 atmrxbyte.c

📁 摩托罗拉Motolola公司网络处理器C3的示范代码.实现了ATM的AAL2层交换功能.想了解网络处理器的可以
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    IregANDlit(Temp,0xF0);    Branch(ALWAYS,Upc+1);    Abus(IregsA(Temp));    Bbus(IregsB(CpId));    ALU(OR);    Actions(IregsAwrite);    Branch(ALWAYS,Upc+1);    /* The lowest byte of the key is ready write it to SdpTxMsg->data0 */    CregsAddrWrite(RXBYTECTL + (int) &((RxByteCtrlSpc*)NULL)->reserved+6);    Abus(IregsA(CpId));    ALU(PassA);    Pbus(ALUout);    Actions(CregsWrite);    Branch(ALWAYS, Upc+1);    Abus(IregsA(Temp));    ALU(PassA);    CregsAddrWrite(TXMSG0 + (int) &((SdpTxMsg*)NULL)->data0);    Pbus(ALUout);    Actions(CregsWrite);    Branch(ALWAYS,Upc+1);    /* This finishes the process of constructing the lookup key */LabelDef(PTI_ENCODE);    /* Now look for OAM/RM Cells */    /* VPI = any value, VCI[15:4] = 0 */    DCPSIM_MESSAGE(PTI_ENCODE);    Branch(ALWAYS, Upc+1);#define CamValue        Ireg4    IregsA(CamValue);    Bbus(Literal(0));    ALU(PassB);    Actions(IregsAwrite);    Branch(ALWAYS, Upc+1);    Bbus(IregsB(HdrByte2)); /* HdrByte2 has 0, vci[15:12] */    Abus(Literal(0x0F));    ALU(AND);    IregsA(CamValue);    Actions(IregsAwrite);    Branch(ALWAYS, Upc+1);    Bbus(IregsB(HdrByte3));  /* HdrByte3 has vci[11:4] */    Abus(IregsA(CamValue));    ALU(OR);    Actions(IregsAwrite);    Branch(ALWAYS, Upc+1);    Bbus(IregsB(CamValue));    ALU(XOR);    Abus(IregsA(CamValue));    Actions(IregsAwrite);    /* clear out VCI from 15:4 'or' from CAM */    Branch(ALUzero, Upc+2);  /* If Vci<15:4> is zero skip */    DCPSIM_MESSAGE(VC_GREATERTHAN_15);    Abus(IregsA(CamValue));  /* Set CamValue b7='1' ('OR'of Vci<15:4>)*/    Bbus(Literal(0x80));     /* i.e. set if Vci > 16 */    ALU(OR);    Actions(IregsAwrite);    Branch(ALWAYS, Upc+1);    Bbus(IregsB(HdrByte4));    Abus(IregsA(CamValue));    ALU(OR);                 /* Ireg4  = [xVCI<2:0>,PTIc]  */    Actions(IregsAwrite);    /*          ^='OR' of VCI<15:3> */    Branch(ALWAYS, Upc+1);    CregsAddrWrite(ATM_EXTRACT + (int) &((AtmExtract*)NULL)->camValue);    Abus(IregsA(CamValue));    ALU(PassA);    Actions(CregsWrite);  Pbus(ALUout);    Branch(ALWAYS, Upc+1);    CregsAddrWrite(ATM_EXTRACT + (int) &((AtmExtract*)NULL)->encodedPti);    Branch(ALWAYS, Upc+1);   /* need 2 clocks to set up ireg4 before camming */    /**************************************************************     * The following CAM entries are used to look up PTI combinations.     * The CAM entries themselves for the 9 bit cam have the following     * match value format:     *     *  +----+----+----+----+----+----+----+----+     *  |VCI |   VCI[2:0]   |     PTI      |  X |     *  |<6  |              |              |    |     *  +----+----+----+----+----+----+----+----+     *     ^                                (clp)     *     |     *     +--- 0 = VCI<6, 1 = VCI>=6     *     * This will be driven from IREG4 as selected in the status reg     * and assumes Hardware applies 0's to bits 9 and 10.     *****************************************************************/    /* F4 OAM ? */    CAMMATCH("x0011xxxx", -1, F4S_CELL); /* VCI 3 */    CAMMATCH("x0100xxxx", -1, F4E_CELL); /* VCI 4 */    Branch(CAMboolean, Label(TAG_XLAT));    /* F5 OAM, RM ? */    CAMMATCH("xxxxx100x", -1, F5S_CELL); /* PTI=4 */    CAMMATCH("xxxxx101x", -1, F5E_CELL); /* PTI=5 */    CAMMATCH("xxxxx110x", -1, RM_CELL);  /* PTI 6 - VP RM and VC RM cells */    Branch(CAMboolean, Label(TAG_XLAT));LabelDef(USER_CELL_FOUND);          /* else, user cell found */    DCPSIM_MESSAGE(CAM_MISS);    Abus(Literal(USER_CELL));       /* No, this is a UserCell */    ALU(PassA);    Actions(CregsWrite);    Pbus(ALUout);    Branch(ALWAYS, Upc+1);    Branch(ALWAYS, Label(EXTRACT_HDR_STATUS));LabelDef(TAG_XLAT);    DCPSIM_MESSAGE(CAM_HIT);    Bbus(CAMtag);    ALU(PassB);    Actions(CregsWrite);    Pbus(ALUout);    Branch(ALWAYS, Upc+1);#undef Temp#undef CpId#undef HdrByte1#undef HdrByte2#undef HdrByte3#undef HdrByte4/************************************************************** * Status can be: *     1. 0x00 = Good HEC Cell (Payload) *     2. 0x01 = Idle Cell (No Payload) *     3. 0x80 = Bad HEC Cell (No payload) **************************************************************/LabelDef(EXTRACT_HDR_STATUS);#undef CamValue#define Temp4 Ireg4    CregsAddrWrite(ATM_EXTRACT + (int) &((AtmExtract*)NULL)->pduHdrStatus);    Abus(Payload);    ALU(PassA);    IregsA(Temp4);    Actions(CregsWrite + IregsAwrite + UnloadFIFO);    Pbus(ALUout);    Branch(ALWAYS, Upc+1);    DCPSIM_MESSAGE(HDR_STATUS);    Abus(IregsA(Temp4));    Bbus(Literal(IDLE_UA_CELL));    ALU(XOR);    Branch(ALWAYS, Upc+1);    Branch(ALUzero, Label(AWAIT_MERGE9_IDLE));/* * If we're in OC12c, pass the token at this point. Passing * the token here gives the next channel processor enough time * to get the token and find the next user cell in order * to send it up. All other processors without the token are dropping * the current cell. * * In OC3c, all CPs always own their token so the following * token passing code does nothing. * * In OC12 non-concatenated, we must not use the token at * all to determine how to dispose of a cell. The following * code segment is skipped for OC12 non-concatenated. */#ifndef OC12    Abus(IregsA(STATUSreg));            /* then lower it */    Bbus(Literal(TOKEN));               /* Give up token, assume model */    ALU(OR);                            /* where we raise it for one clock */    Actions(IregsAwrite);    Branch(ALWAYS, Upc+1);    Abus(IregsA(STATUSreg));    Bbus(Literal(~TOKEN));              /* Drop Token Flag */    ALU(AND);    Actions(IregsAwrite);    Branch(ALWAYS, Upc+1);#endif    CregsAddrWrite(RXSTATUS);    Branch(ALWAYS, Upc+1);    DCPSIM_MESSAGE(HEADER_COMPLETE);    Abus(Literal(P1_FLG));    ALU(PassA);    Actions(CregsWrite);    Pbus(ALUout);    Branch(ALWAYS, Upc+1);    Abus(IregsA(Temp4));    Bbus(Literal(BAD_HEC_CELL));    ALU(XOR);    Branch(ALWAYS, Upc+1);    Branch(ALUzero, Label(AWAIT_MERGE9_BAD));LabelDef(LAUNCH_VCC_LOOKUP);    DCPSIM_MESSAGE(LAUNCH_LOOKUP);    CregsAddrWrite(TXMSG0 + (int)&((SdpTxMsg*)NULL)->avail);    Branch(ALWAYS, Upc+1);    Abus(Literal(LAUNCH_RB_REQ));        /* Launch request */    ALU(PassA);    Pbus(ALUout);    Actions(CregsWrite);    Branch(ALWAYS, Upc+1);LabelDef(PAYLOAD_PROCESS);    LatchPayload(Temp4, UseAbus);    Actions(UnloadFIFO + DataOutValid + RepeatUntil);    Pbus(Payload);    Branch(Data9, Upc+1);    /* A single byte following the payload indicates the success/failure     * of the 10 bit CRC (used to validate the payload of OAM cells)     */LabelDef(REPORT_CRC10_STATUS);    DCPSIM_MESSAGE(PAYLOAD_RECEIVED_REPORT_CRC10);    CregsAddrWrite(ATM_EXTRACT + (int) &((AtmExtract*)NULL)->crc10Indicator);    Branch(ALWAYS, Upc+1);    Abus(IregsA(Temp4));    ALU(PassA);    Actions(CregsWrite);    Pbus(ALUout);    Branch(ALWAYS, Upc+1);    /*     * Bug1040 - after last byte of data sent (we crossed 16 byte line     * boundary) to the SDP DMA engine, we need to stall for 10 clocks     * before changing scopes or the last byte will be written to the wrong     * scope.  Stall here.     */    Branch(ALWAYS, Upc+1);    Branch(ALWAYS, Upc+1);    Branch(ALWAYS, Upc+1);    Branch(ALWAYS, Upc+1);    Branch(ALWAYS, Upc+1);    Branch(ALWAYS, Upc+1);    Branch(ALWAYS, Label(GIVE_EXTRACT_TO_RC));LabelDef(AWAIT_MERGE9_IDLE);    DCPSIM_MESSAGE(GOT_IDLE);    Branch(ALWAYS, Upc+1);    Actions(UnloadFIFO + RepeatUntil);    Branch(Data9, Label(EXTRACT_START));LabelDef(AWAIT_MERGE9_BAD);    DCPSIM_MESSAGE(GOT_BAD_HEC);    Branch(ALWAYS, Upc+1);    Actions(UnloadFIFO + RepeatUntil);    Branch(Data9, Upc+1);LabelDef(GIVE_EXTRACT_TO_RC);    DCPSIM_MESSAGE(SWITCH);    CregsAddrWrite(RXSTATUS);           /* Done, Set Status */    Branch(ALWAYS, Upc+1);    Abus(Literal(P1_FLG));    ALU(PassA);    Actions(CregsWrite+Merge9+DataOutValid);    Pbus(ALUout);    Branch(ALWAYS, Upc+1);    Branch(ALWAYS, Label(NEXT_EXTRACT));}

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