atmrxbyte.c

摩托罗拉Motolola公司网络处理器C3的示范代码.实现了ATM的AAL2层交换功能.想了解网络处理器的可以

/*****************************************************************************
 * Copyright (c) 2000,2001, 2002 C-Port Corporation,A Motorola Company
 * All Rights Reserved
 *
 * The information contained in this file is confidential and proprietary.
 * Any reproduction, use or disclosure, in whole or in part, of this
 * program, including any attempt to obtain a human-readable version of this
 * program, without the express, prior written consent of C-Port
 * Corporation or Motorola Incorporated is strictly prohibited.
 *
 * File :  RxByte.c
 *****************************************************************************/

#define RXBYTE
#include "sdpUcode.h"
#include "dcpRegistersCp.h"
#include "rcSdpAtmApiIf.h"
#include "rbDefs.h"
#include <stdio.h>

#define EXTRACT   ((int) &((SdpRxCregs*)NULL)->extract)
#define RXSTATUS  ((int) &((SdpRxCregs*)NULL)->rxStatus)
#define RXBYTECTL ((int) &((SdpRxCregs*)NULL)->rxCtl.byte)
#define TXMSG0    ((int) &((SdpRxCregs*)NULL)->txMsg[0])
#define ATM_EXTRACT (EXTRACT + (int) &((ExtractSpc*)NULL)->atmExtract)

#define P1_FLG        (RXSTATUS_P1DONE >> 8)
#define RC_OWN_FLG    (RXSTATUS_OWN    >> 8)

void
SDPmain()
{
Description = ("ATM Ucode for the SDP RX Byte Processor.");

#define CngstnCnt       Ireg0   /*  Indicates how many cells have dropped since
                                 *  the RC gave extract space back to the SDP
                                 *  This register is available when we have extract
                                 *  space and after we have written the value to the RC
                                 */

/******************************************************************************
 * RxByte Functionality
 *
 * The RxByte code receives both good and bad cells from the rxSync
 * processor.  Good cells are indicated with a 0 replacing the HEC, bad
 * HEC cells are indicated with a negative value and idle/unassigned HECs
 * are replaced with a 1.  No payload is transmitted by the sync processor
 * for idle/unassigned/bad cells.  All cells are terminated with data9.
 * The rxSync processor checks OAM CRC-10 on all cells forwarded with
 * payload.  Status is sent (0/-1) with the data9 byte after the payload.
 *
 *******************************************************************************
 * Need to add:
 * 1.  OC12c functionality at line rate - this will not work in hardware until   *     D00 (due to FIFO issues), but we have 2 clocks per byte at OC12c rates.
 * 2.  VPC TLU lookup,VpcIndex generation
 *******************************************************************************
 */



LabelDef(COLD_START);

    Abus(IregsA(STATUSreg));
    Bbus(Literal(CAMSRC));   /* CAM sourced from Ireg4 */
    ALU(PassB);
    Actions(IregsAwrite);
    Branch(ALWAYS, Upc+1);

LabelDef(NEXT_EXTRACT);

/* OC12 non-concatenated must not pass the token. The
 * token mechanism is enabled whenever aggregation mode
 * is turned on the SDP_MODE3. Because OC12 is aggregated
 * at the RxBit interface but really an OC3c stream
 * here in RxByte, no token passing is necessary.
 * We get away with passing the token in OC3c because
 * the hardware forces all CPs to always own their
 * token when aggregation is disabled.
 */

    Branch(AggToken,Label(SETUP_RXSTATUS));
    Actions(UnloadFIFO + RepeatUntil);
    Branch(Data9,Label(NEXT_EXTRACT));

LabelDef(SETUP_RXSTATUS);

    IregInit(CngstnCnt, 0x00, UseAbus);
    Branch(ALWAYS, Upc+1);

    CregsAddrWrite(RXSTATUS);
    Branch(ALWAYS, Upc+1);

    Branch(ALWAYS, Upc+1);

LabelDef(EXTRACT_POLL_LOOP);

    Abus(Creg);
    ALU(PassA);
    Branch(ALWAYS, Upc+1);

    Actions(InvertCondition);
    Branch(ALUneg, Label(EXTRACT_START));

    Actions(InvertCondition);
    Branch(RxDataValid, Label(EXTRACT_POLL_LOOP));

LabelDef(CONGESTION_DUMP_PDU);

    DCPSIM_MESSAGE(CONGESTED_DROPPED_CELL);
    Abus(IregsA(CngstnCnt));
    Bbus(Literal(0x01));
    ALU(ADD);
    Actions(IregsAwrite);
    Branch(ALWAYS, Upc+1);

    Actions(UnloadFIFO + RepeatUntil);
    Branch(Data9, Label(EXTRACT_POLL_LOOP));

/******************************************************************************
 *                              VCC Lookup
 ******************************************************************************
 * RxByte performs a VCC lookup using the following algorithm.
 * It first generates a 32-bit key for the TLU lookup.
 * The lower 4 bits of the lookup-key indicate the port (i.e. CpId).
 *
 *
 *  The key is calculated as shown below
 *
 *            +--------------+---------------------+-------+
 *            |   VPI        |       VCI           | CPID  |
 *            +--------------+---------------------+-------+
 *            31             20                    4       0
 *
 *            data3 VPI<11:4>          in case of NNI
 *                  <0000>,VPI<7:4>    in case of UNI
 *            data2 VPI<3:0>,VCI<15:12>
 *            data1 VCI<11:4>
 *            data0 VCI<3:0>,CPID<3:0>
 *
 *  Note: The following code assumes UNI interface.
 *
 *****************************************************************************/

#define HdrByte1        Ireg1
#define HdrByte2        Ireg2
#define HdrByte3        Ireg3
#define HdrByte4        Ireg5
#define Temp            Ireg6  /* Temporary register */
#define CpId            Ireg8



LabelDef(EXTRACT_START);

    DCPSIM_MESSAGE(HAVE_SCOPE);
    CregsAddrWrite(ATM_EXTRACT + (int) &((AtmExtract*)NULL)->congestionDrops);
    Abus(IregsA(CngstnCnt));
    ALU(PassA);
    Pbus(ALUout);
    Actions(CregsWrite);
    Branch(ALWAYS, Upc+1);

#undef  CngstnCnt

    DCPSIM_MESSAGE(GET_CPID);
    CregsAddrWrite(RXBYTECTL + (int) &((RxByteCtrlSpc*)NULL)->cpId_tblId);
    Branch(ALWAYS, Upc+1);

    Branch(ALWAYS, Upc+1);

    Bbus(Literal(0xF0));
    Abus(Creg);              /* Initialize Key with cpId */
    ALU(AND);                /* It is of form [<cpId>, <tblId>] */
    IregsA(CpId);
    Actions(IregsAwrite);
    Branch(ALWAYS, Upc+1);

    Bbus(IregsB(CpId));
    ALU(RotateB(4));
    IregsA(Temp);
    Actions(IregsAwrite);
    Branch(ALWAYS,Upc+1);

    CregsAddrWrite(RXBYTECTL + (int) &((RxByteCtrlSpc*)NULL)->reserved+3);
    Abus(IregsA(Temp));
    ALU(PassA);
    Pbus(ALUout);
    Actions(CregsWrite);
    Branch(ALWAYS, Upc+1);

    Bbus(IregsB(Temp));
    ALU(PassB);
    IregsA(CpId);
    Actions(IregsAwrite);
    Branch(ALWAYS, Upc+1);

LabelDef(EXTRACT_HDR1);

    CregsAddrWrite(ATM_EXTRACT + (int) &((AtmExtract*)NULL)->cellHeader);
    LatchPayload(HdrByte1, UseAbus); /* HdrByte1 GFC<3:0>,VPI<7:4> */
    Actions(UnloadFIFO);             /* UNLOAD */
    Branch(ALWAYS, Upc+1);

    DCPSIM_MESSAGE(HDR1);            /* Write first byte to extract space */
    Abus(IregsA(HdrByte1));
    ALU(PassA);
    Pbus(ALUout);
    Actions(CregsWrite);
    Branch(ALWAYS, Upc+1);


    Bbus(IregsB(HdrByte1));
    Abus(Literal(0x0F));
    ALU(AND);
    IregsA(Temp);
    Actions(IregsAwrite);
    Branch(ALWAYS,Upc+1);


    /* Now the highest byte of the key is ready. Write it to SdpTxMsg->data3*/

    Abus(IregsA(Temp));
    ALU(PassA);
    CregsAddrWrite(TXMSG0 + (int) &((SdpTxMsg*)NULL)->data3);
    Pbus(ALUout);
    Actions(CregsWrite);
    Branch(ALWAYS, Upc+1);

LabelDef(EXTRACT_HDR2);
    CregsAddrWrite(ATM_EXTRACT + (int) &((AtmExtract*)NULL)->cellHeader+1);
    LatchPayload(HdrByte2, UseAbus);  /* HdrByte2 is VPI<3:0>,VCI<15:12> */
    Actions(UnloadFIFO);              /* UNLOAD */
    Branch(ALWAYS, Upc+1);

    DCPSIM_MESSAGE(HDR2);    /* Write second byte of header to extract space */
    Abus(IregsA(HdrByte2));
    ALU(PassA);
    Pbus(ALUout);
    Actions(CregsWrite);
    Branch(ALWAYS, Upc+1);


    /* Next higher byte of the key is ready write it to SdpTxMsg->data2 */

    Abus(IregsA(HdrByte2));
    ALU(PassA);
    CregsAddrWrite(TXMSG0 + (int) &((SdpTxMsg*)NULL)->data2);
    Pbus(ALUout);
    Actions(CregsWrite);
    Branch(ALWAYS,Upc+1);


LabelDef(EXTRACT_HDR3);
    CregsAddrWrite(ATM_EXTRACT + (int) &((AtmExtract*)NULL)->cellHeader+2);
    LatchPayload(HdrByte3, UseAbus);  /* HdrByte3 is VCI<11:4> */
    Actions(UnloadFIFO);              /* UNLOAD */
    Branch(ALWAYS, Upc+1);

    DCPSIM_MESSAGE(HDR3);     /* write third  byte of header to extractspace */
    Abus(IregsA(HdrByte3));
    ALU(PassA);
    Pbus(ALUout);
    Actions(CregsWrite);
    Branch(ALWAYS, Upc+1);


    /* Next higher byte of the key is ready write it to SdpTxMsg->data1 */

    Abus(IregsA(HdrByte3));
    ALU(PassA);
    CregsAddrWrite(TXMSG0 + (int) &((SdpTxMsg*)NULL)->data1);
    Pbus(ALUout);
    Actions(CregsWrite);
    Branch(ALWAYS,Upc+1);


LabelDef(EXTRACT_HDR4);
    CregsAddrWrite(ATM_EXTRACT + (int) &((AtmExtract*)NULL)->cellHeader+3);
    LatchPayload(HdrByte4, UseAbus); /* HdrByte4 is VCI<3:0>,PTI<2:0>,CLP<0> */
    Actions(UnloadFIFO);             /* UNLOAD */
    Branch(ALWAYS, Upc+1);

    DCPSIM_MESSAGE(HDR4);
    Abus(IregsA(HdrByte4));  /* Write fourth byte of header to extract space */
    ALU(PassA);
    Pbus(ALUout);
    Actions(CregsWrite);
    Branch(ALWAYS, Upc+1);


    Bbus(IregsB(HdrByte4));
    ALU(PassB);
    IregsA(Temp);
    Actions(IregsAwrite);
    Branch(ALWAYS,Upc+1);