📄 arm-asm-disasm-test.f
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\ ----------------------------------------------------------------------------
\ Tests which generate random (or sequential) op-codes and check that
\ assembler and disassembler are consistant with each other...
ALSO ARM-DISASSEMBLER ALSO ARM-ASSEMBLER ALSO PRIVATE-WORDLIST ALSO FORTH
VARIABLE RANDOM-SEED
1 RANDOM-SEED !
: RANDOM ( -- x )
RANDOM-SEED @ 10DCD * 1+ DUP RANDOM-SEED ! ;
: H. ( u -- ) \ Display u in hex
BASE @ >R
HEX 0 <# # # # # # # # # #>
R> BASE !
TYPE SPACE
;
: CLEANUP-OP ( x1 -- x2 ) \ Make op-code unambiguous
DUP 0E000000 AND 02000000 =
IF
\ make data literal match format used by assembler
DUP FFFFF000 AND SWAP
DUP 0FF AND
SWAP F00 AND 7 RSHIFT RROTATE
ARM-DATA-LITERAL
OR
THEN
DUP 0E000FFF AND 04000000 =
IF
01800000 OR \ Force 0 index to be pre up index
THEN
DUP 0E0000FF AND 0C000000 =
IF
01800000 OR \ Force 0 index to be pre up index
THEN
DUP 0E400F9F AND 00400090 =
IF
01800000 OR \ Force 0 index to be pre up index
THEN
DUP FFF801C0 AND F1080000 =
IF
000001C0 OR \ Force iflags in CPSIE/ID to be not zero
THEN
DUP 0DB00000 AND 01200000 =
IF
000F0000 OR \ Force field_mask in MSR to be not zero
THEN
DUP 0F8000F0 AND 06800070 =
IF
FFFFFCFF AND \ Force SBZ fields in extend instructions
THEN
;
\ : BREAKPOINT ." BREAKPOINT" QUIT ;
: TEST ( -- ) \ Test assembler and disassembler are consistant with each other
CODE-HERE 3 + 3 INVERT AND CODE-HERE!
ALSO ARM-ASSEMBLER
1 \ true for random instructions, false for all instructions in sequence
DUP IF -10000 \ Test 10000 (hex) random instructions
ELSE D0000000 \ Test all instruction D0000000-FFFFFFFF
THEN
>R
BEGIN
DUP IF RANDOM
ELSE R@ DUP FFF AND 0= IF DUP H. CR THEN
THEN
CLEANUP-OP >R
CODE-HERE R@
DEPTH >R
ARM-DISASM-OP
DEPTH R> <> IF ." DISASM STACK DEPTH MISMATCH " R@ H. .S BREAKPOINT THEN
\ R@ FF AND 0= IF 2DUP TYPE CR THEN
\ 2DUP TYPE CR \ KEY DROP
2DUP S" UNDEFINED" EQUAL 0=
IF
DEPTH >R
CODE-HERE >R
0 CODE-HERE !
CODE-HERE CODE-ORIGIN !
OP-RESET
2DUP ['] EVALUATE CATCH ?DUP IF ." EXCEPTION " . KEY DROP THEN
OP-END
CODE-HERE 1 CELLS - R@ <> IF ." CODE-HERE MISMATCH" R@ H. CODE-HERE H. CR TYPE BREAKPOINT THEN
R> CODE-HERE!
DEPTH R> <> IF ." ASM STACK DEPTH MISMATCH " R@ H. .S BREAKPOINT THEN
R@ CODE-HERE @ <>
IF
\ assembler didn't produce same op-code as was disassembled...
UNPREDICTABLE @
IF
R@ CODE-HERE @ XOR \ bits which differ
UNPREDICTABLE @ INVERT AND
IF ." UNPREDICTABLE FAIL " UNPREDICTABLE @ H. R@ H. CODE-HERE H. BREAKPOINT THEN
\ 2DUP TYPE CR
ELSE
." FAIL "
CODE-HERE H. R@ H. CODE-HERE @ H.
2DUP TYPE CR
BREAKPOINT
THEN
THEN
THEN
2DROP
R> DROP
R> 1+ DUP >R
0=
UNTIL
R> DROP
PREVIOUS
;
\ ----------------------------------------------------------------------------
\ Words to test specific test cases...
: QUOTE ( c-addr u -- c-addr u ) \ display string in double quotes
[CHAR] " EMIT 2DUP TYPE [CHAR] " EMIT SPACE
;
: >" ( x "ccc"<quote> -- )
BASE @ >R HEX
>R
[CHAR] " PARSE
R@ H. QUOTE CR
0 R@ DEPTH >R
ARM-DISASM-OP
DEPTH R> <> IF CR ." DISASM STACK DEPTH FAIL " .S KEY DROP THEN
9 SPACES QUOTE
2OVER EQUAL 0= IF CR ." DISASM FAIL" KEY DROP THEN
DEPTH >R
ALSO ARM-ASSEMBLER
0 CODE-ORIGIN !
OP-RESET
['] EVALUATE CATCH ?DUP IF ." EXCEPTION " . KEY DROP THEN OP-VALUE @
PREVIOUS
R> DEPTH <> IF CR ." ASM STACK DEPTH FAIL " .S KEY DROP THEN
DUP H. CR
R> <> IF CR ." ASM FAIL" KEY DROP THEN
R> BASE !
;
PREVIOUS PREVIOUS PREVIOUS PREVIOUS
\ ----------------------------------------------------------------------------
\ Test cases...
.( TEST CASES ) CR CR
00a21003 >" adc eq r1 r2 r3"
10a21003 >" adc ne r1 r2 r3"
20a21003 >" adc cs r1 r2 r3" \ also hs
30a21003 >" adc cc r1 r2 r3" \ also lo
40a21003 >" adc mi r1 r2 r3"
50a21003 >" adc pl r1 r2 r3"
60a21003 >" adc vs r1 r2 r3"
70a21003 >" adc vc r1 r2 r3"
80a21003 >" adc hi r1 r2 r3"
90a21003 >" adc ls r1 r2 r3"
a0a21003 >" adc ge r1 r2 r3"
b0a21003 >" adc lt r1 r2 r3"
c0a21003 >" adc gt r1 r2 r3"
d0a21003 >" adc le r1 r2 r3"
e0a21003 >" adc r1 r2 r3" \ also al
c0a21003 >" adc gt r1 r2 r3"
c0b21003 >" adc gt s r1 r2 r3"
c0a21203 >" adc gt r1 r2 r3 lsl 4 #"
c0a21413 >" adc gt r1 r2 r3 lsl r4"
c0a21023 >" adc gt r1 r2 r3 lsr 20 #"
c0a21223 >" adc gt r1 r2 r3 lsr 4 #"
c0a21433 >" adc gt r1 r2 r3 lsr r4"
c0a21043 >" adc gt r1 r2 r3 asr 20 #"
c0a21243 >" adc gt r1 r2 r3 asr 4 #"
c0a21453 >" adc gt r1 r2 r3 asr r4"
c0a21263 >" adc gt r1 r2 r3 ror 4 #"
c0a21fe3 >" adc gt r1 r2 r3 ror 1F #"
c0a21473 >" adc gt r1 r2 r3 ror r4"
c0a21063 >" adc gt r1 r2 r3 rrx"
c2a21034 >" adc gt r1 r2 34 #"
c2b21034 >" adc gt s r1 r2 34 #"
c2acb034 >" adc gt r11 r12 34 #"
c2a21fff >" adc gt r1 r2 3FC #"
c2a211ff >" adc gt r1 r2 -3FFFFFC1 #"
c0821003 >" add gt r1 r2 r3"
c0021003 >" and gt r1 r2 r3"
ca000000 >" b gt 8 #"
cafffffc >" b gt FFFFFFF8 #"
cb000000 >" bl gt 8 #"
cbfffffc >" bl gt FFFFFFF8 #"
c1c21003 >" bic gt r1 r2 r3"
e1212374 >" bkpt 1234 #" \ ARM 5
e12fed7c >" bkpt 0FEDC #"
fa000000 >" blx 8 #" \ ARM 5
fafffffc >" blx FFFFFFF8 #"
fb000000 >" blx 0A #"
fbfffffc >" blx FFFFFFFA #"
c12fff31 >" blx gt r1" \ ARM 5
c12fff3b >" blx gt r11"
c12fff11 >" bx gt r1" \ ARM 4T + 5
c12fff1b >" bx gt r11"
c12fff21 >" bxj gt r1" \ ARM 5J + 6
c12fff2b >" bxj gt r11"
ce2431c5 >" cdp gt p1 2 # c3 c4 c5 6 #"
ce534622 >" cdp gt p6 5 # c4 c3 c2 1 #"
fe2431c5 >" cdp2 p1 2 # c3 c4 c5 6 #" \ ARM 5
c16f1f12 >" clz gt r1 r2" \ ARM 5
c16fbf1c >" clz gt r11 r12"
c1710002 >" cmn gt r1 r2"
c17b000c >" cmn gt r11 r12"
c1510002 >" cmp gt r1 r2"
c15b000c >" cmp gt r11 r12"
c0221003 >" eor gt r1 r2 r3"
cd932100 >" ldc gt p1 c2 [ r3 ]"
cd93c100 >" ldc gt p1 c12 [ r3 ]"
cd9d2100 >" ldc gt p1 c2 [ r13 ]"
cd932b00 >" ldc gt p11 c2 [ r3 ]"
cc932104 >" ldc gt p1 c2 [ r3 ] { 4 # }"
cc9321ff >" ldc gt p1 c2 [ r3 ] { 0FF # }"
ccd32104 >" ldc gt l p1 c2 [ r3 ] { 4 # }"
cc332104 >" ldc gt p1 c2 [ r3 ] -10 #"
ccb32104 >" ldc gt p1 c2 [ r3 ] 10 #"
cc732104 >" ldc gt l p1 c2 [ r3 ] -10 #"
ccf32104 >" ldc gt l p1 c2 [ r3 ] 10 #"
cd132104 >" ldc gt p1 c2 [ r3 -10 # ]"
cd932104 >" ldc gt p1 c2 [ r3 10 # ]"
cd532104 >" ldc gt l p1 c2 [ r3 -10 # ]"
cdd32104 >" ldc gt l p1 c2 [ r3 10 # ]"
cd332104 >" ldc gt p1 c2 [ r3 -10 # ] !"
cdb32104 >" ldc gt p1 c2 [ r3 10 # ] !"
cd732104 >" ldc gt l p1 c2 [ r3 -10 # ] !"
cdf32104 >" ldc gt l p1 c2 [ r3 10 # ] !"
fd932100 >" ldc2 p1 c2 [ r3 ]"
c8110004 >" ldm gt da r1 { r2 }"
c9110004 >" ldm gt db r1 { r2 }"
c8910004 >" ldm gt ia r1 { r2 }"
c9910004 >" ldm gt ib r1 { r2 }"
c811800c >" ldm gt da r1 { r2 r3 pc }"
c81e800c >" ldm gt da lr { r2 r3 pc }"
c8110000 >" ldm gt da r1 { }" \ unpredictable
c8310004 >" ldm gt da r1 ! { r2 }"
c831800c >" ldm gt da r1 ! { r2 r3 pc }"
c8510004 >" ldm gt da r1 { r2 } ^"
c9510004 >" ldm gt db r1 { r2 } ^"
c8d10004 >" ldm gt ia r1 { r2 } ^"
c9d10004 >" ldm gt ib r1 { r2 } ^"
c871000c >" ldm gt da r1 ! { r2 r3 } ^" \ unpredictable
c871800c >" ldm gt da r1 ! { r2 r3 pc } ^"
c5921000 >" ldr gt r1 [ r2 ]"
c59cb000 >" ldr gt r11 [ r12 ]"
c5921004 >" ldr gt r1 [ r2 4 # ]"
c5921fff >" ldr gt r1 [ r2 0FFF # ]"
c5121004 >" ldr gt r1 [ r2 -4 # ]"
c7921003 >" ldr gt r1 [ r2 r3 ]"
c792100d >" ldr gt r1 [ r2 r13 ]"
c7121003 >" ldr gt r1 [ r2 -r3 ]"
c7921083 >" ldr gt r1 [ r2 r3 lsl 1 # ]"
c7921f83 >" ldr gt r1 [ r2 r3 lsl 1F # ]"
c79210a3 >" ldr gt r1 [ r2 r3 lsr 1 # ]"
c7921023 >" ldr gt r1 [ r2 r3 lsr 20 # ]"
c79210c3 >" ldr gt r1 [ r2 r3 asr 1 # ]"
c79210e3 >" ldr gt r1 [ r2 r3 ror 1 # ]"
c7921063 >" ldr gt r1 [ r2 r3 rrx ]"
c7121083 >" ldr gt r1 [ r2 -r3 lsl 1 # ]"
c5b21004 >" ldr gt r1 [ r2 4 # ] !"
c5b21fff >" ldr gt r1 [ r2 0FFF # ] !"
c5321004 >" ldr gt r1 [ r2 -4 # ] !"
c7b21003 >" ldr gt r1 [ r2 r3 ] !"
c7b2100d >" ldr gt r1 [ r2 r13 ] !"
c7321003 >" ldr gt r1 [ r2 -r3 ] !"
c7b21083 >" ldr gt r1 [ r2 r3 lsl 1 # ] !"
c7b210a3 >" ldr gt r1 [ r2 r3 lsr 1 # ] !"
c7b210c3 >" ldr gt r1 [ r2 r3 asr 1 # ] !"
c7b210e3 >" ldr gt r1 [ r2 r3 ror 1 # ] !"
c7b21063 >" ldr gt r1 [ r2 r3 rrx ] !"
c7321083 >" ldr gt r1 [ r2 -r3 lsl 1 # ] !"
c4921004 >" ldr gt r1 [ r2 ] 4 #"
c4921fff >" ldr gt r1 [ r2 ] 0FFF #"
c4121004 >" ldr gt r1 [ r2 ] -4 #"
c6921003 >" ldr gt r1 [ r2 ] r3"
c692100d >" ldr gt r1 [ r2 ] r13"
c6121003 >" ldr gt r1 [ r2 ] -r3"
c6921083 >" ldr gt r1 [ r2 ] r3 lsl 1 #"
c69210a3 >" ldr gt r1 [ r2 ] r3 lsr 1 #"
c69210c3 >" ldr gt r1 [ r2 ] r3 asr 1 #"
c69210e3 >" ldr gt r1 [ r2 ] r3 ror 1 #"
c6921063 >" ldr gt r1 [ r2 ] r3 rrx"
c6121083 >" ldr gt r1 [ r2 ] -r3 lsl 1 #"
c4b21000 >" ldr gt t r1 [ r2 ]"
c4b21004 >" ldr gt t r1 [ r2 ] 4 #"
c6b21003 >" ldr gt t r1 [ r2 ] r3"
c6b21083 >" ldr gt t r1 [ r2 ] r3 lsl 1 #"
c4321004 >" ldr gt t r1 [ r2 ] -4 #"
c6321003 >" ldr gt t r1 [ r2 ] -r3"
c6321083 >" ldr gt t r1 [ r2 ] -r3 lsl 1 #"
c5d21000 >" ldr gt b r1 [ r2 ]"
c5d21004 >" ldr gt b r1 [ r2 4 # ]"
c7d21083 >" ldr gt b r1 [ r2 r3 lsl 1 # ]"
c5f21004 >" ldr gt b r1 [ r2 4 # ] !"
c7f21003 >" ldr gt b r1 [ r2 r3 ] !"
c7f21003 >" ldr gt b r1 [ r2 r3 ] !"
c4d21004 >" ldr gt b r1 [ r2 ] 4 #"
c6d21003 >" ldr gt b r1 [ r2 ] r3"
c6d21083 >" ldr gt b r1 [ r2 ] r3 lsl 1 #"
c5521004 >" ldr gt b r1 [ r2 -4 # ]"
c7521083 >" ldr gt b r1 [ r2 -r3 lsl 1 # ]"
c5721004 >" ldr gt b r1 [ r2 -4 # ] !"
c7721003 >" ldr gt b r1 [ r2 -r3 ] !"
c7721003 >" ldr gt b r1 [ r2 -r3 ] !"
c4521004 >" ldr gt b r1 [ r2 ] -4 #"
c6521003 >" ldr gt b r1 [ r2 ] -r3"
c6521083 >" ldr gt b r1 [ r2 ] -r3 lsl 1 #"
c4f21000 >" ldr gt bt r1 [ r2 ]"
c4f21004 >" ldr gt bt r1 [ r2 ] 4 #"
c6f21003 >" ldr gt bt r1 [ r2 ] r3"
c6f21083 >" ldr gt bt r1 [ r2 ] r3 lsl 1 #"
c4721004 >" ldr gt bt r1 [ r2 ] -4 #"
c6721003 >" ldr gt bt r1 [ r2 ] -r3"
c6721083 >" ldr gt bt r1 [ r2 ] -r3 lsl 1 #"
c1d210b0 >" ldr gt h r1 [ r2 ]" \ ARM4
c1d210bf >" ldr gt h r1 [ r2 0F # ]"
c1d21fb0 >" ldr gt h r1 [ r2 0F0 # ]"
c15210bf >" ldr gt h r1 [ r2 -F # ]"
c1521fb0 >" ldr gt h r1 [ r2 -F0 # ]"
c19210b3 >" ldr gt h r1 [ r2 r3 ]"
c19210bd >" ldr gt h r1 [ r2 r13 ]"
c11210b3 >" ldr gt h r1 [ r2 -r3 ]"
c1f210bf >" ldr gt h r1 [ r2 0F # ] !"
c17210bf >" ldr gt h r1 [ r2 -F # ] !"
c1b210b3 >" ldr gt h r1 [ r2 r3 ] !"
c13210b3 >" ldr gt h r1 [ r2 -r3 ] !"
c0d210bf >" ldr gt h r1 [ r2 ] 0F #"
c05210bf >" ldr gt h r1 [ r2 ] -F #"
c09210b3 >" ldr gt h r1 [ r2 ] r3"
c01210b3 >" ldr gt h r1 [ r2 ] -r3"
c1d210f0 >" ldr gt sh r1 [ r2 ]" \ ARM4
c1d210ff >" ldr gt sh r1 [ r2 0F # ]"
c1d21ff0 >" ldr gt sh r1 [ r2 0F0 # ]"
c15210ff >" ldr gt sh r1 [ r2 -F # ]"
c1521ff0 >" ldr gt sh r1 [ r2 -F0 # ]"
c19210f3 >" ldr gt sh r1 [ r2 r3 ]"
c19210fd >" ldr gt sh r1 [ r2 r13 ]"
c11210f3 >" ldr gt sh r1 [ r2 -r3 ]"
c1f210ff >" ldr gt sh r1 [ r2 0F # ] !"
c17210ff >" ldr gt sh r1 [ r2 -F # ] !"
c1b210f3 >" ldr gt sh r1 [ r2 r3 ] !"
c13210f3 >" ldr gt sh r1 [ r2 -r3 ] !"
c0d210ff >" ldr gt sh r1 [ r2 ] 0F #"
c05210ff >" ldr gt sh r1 [ r2 ] -F #"
c09210f3 >" ldr gt sh r1 [ r2 ] r3"
c01210f3 >" ldr gt sh r1 [ r2 ] -r3"
c1d210d0 >" ldr gt sb r1 [ r2 ]" \ ARM4
c1d210df >" ldr gt sb r1 [ r2 0F # ]"
c1d21fd0 >" ldr gt sb r1 [ r2 0F0 # ]"
c15210df >" ldr gt sb r1 [ r2 -F # ]"
c1521fd0 >" ldr gt sb r1 [ r2 -F0 # ]"
c19210d3 >" ldr gt sb r1 [ r2 r3 ]"
c19210dd >" ldr gt sb r1 [ r2 r13 ]"
c11210d3 >" ldr gt sb r1 [ r2 -r3 ]"
c1f210df >" ldr gt sb r1 [ r2 0F # ] !"
c17210df >" ldr gt sb r1 [ r2 -F # ] !"
c1b210d3 >" ldr gt sb r1 [ r2 r3 ] !"
c13210d3 >" ldr gt sb r1 [ r2 -r3 ] !"
c0d210df >" ldr gt sb r1 [ r2 ] 0F #"
c05210df >" ldr gt sb r1 [ r2 ] -F #"
c09210d3 >" ldr gt sb r1 [ r2 ] r3"
c01210d3 >" ldr gt sb r1 [ r2 ] -r3"
ce4431d5 >" mcr gt p1 2 # r3 c4 c5 6 #"
cea34632 >" mcr gt p6 5 # r4 c3 c2 1 #"
cea34612 >" mcr gt p6 5 # r4 c3 c2 0 #"
fea34612 >" mcr2 p6 5 # r4 c3 c2 0 #"
c0214392 >" mla gt r1 r2 r3 r4"
c0241293 >" mla gt r4 r3 r2 r1"
c0314392 >" mla gt s r1 r2 r3 r4"
c3a01002 >" mov gt r1 2 #"
c1a01002 >" mov gt r1 r2"
c1a0b00c >" mov gt r11 r12"
c1a01182 >" mov gt r1 r2 lsl 3 #"
c1a01312 >" mov gt r1 r2 lsl r3"
c1b01002 >" mov gt s r1 r2"
ce5431d5 >" mrc gt p1 2 # r3 c4 c5 6 #"
ceb34632 >" mrc gt p6 5 # r4 c3 c2 1 #"
ceb34612 >" mrc gt p6 5 # r4 c3 c2 0 #"
feb34612 >" mrc2 p6 5 # r4 c3 c2 0 #"
c10f1000 >" mrs gt r1 cpsr"
c10fb000 >" mrs gt r11 cpsr"
c14f1000 >" mrs gt r1 spsr"
c121f001 >" msr gt cpsr_ c r1"
c122f001 >" msr gt cpsr_ x r1"
c123f001 >" msr gt cpsr_ cx r1"
c124f001 >" msr gt cpsr_ s r1"
c125f001 >" msr gt cpsr_ cs r1"
c126f001 >" msr gt cpsr_ xs r1"
c127f001 >" msr gt cpsr_ cxs r1"
c128f001 >" msr gt cpsr_ f r1"
c129f001 >" msr gt cpsr_ cf r1"
c12af001 >" msr gt cpsr_ xf r1"
c12bf001 >" msr gt cpsr_ cxf r1"
c12cf001 >" msr gt cpsr_ sf r1"
c12df001 >" msr gt cpsr_ csf r1"
c12ef001 >" msr gt cpsr_ xsf r1"
c12ff001 >" msr gt cpsr_ cxsf r1"
c321f001 >" msr gt cpsr_ c 1 #"
c321f0ff >" msr gt cpsr_ c 0FF #"
c161f001 >" msr gt spsr_ c r1"
c361f0ff >" msr gt spsr_ c 0FF #"
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