📄 arm-asm.f
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INSTRUCTIOND# and \ ARM Assembler, data processing instruction
E0000000 , 0DE00000 , 0800100C , ' DATA# , F2100FFF ,
INSTRUCTIOND# eor \ ARM Assembler, data processing instruction
E0200000 , 0DE00000 , 0800100C , ' DATA# , F2100FFF ,
INSTRUCTIOND# sub \ ARM Assembler, data processing instruction
E0400000 , 0DE00000 , 0800100C , ' DATA# , F2100FFF ,
INSTRUCTIOND# rsb \ ARM Assembler, data processing instruction
E0600000 , 0DE00000 , 0800100C , ' DATA# , F2100FFF ,
INSTRUCTIOND# add \ ARM Assembler, data processing instruction
E0800000 , 0DE00000 , 0800100C , ' DATA# , F2100FFF ,
INSTRUCTIOND# adc \ ARM Assembler, data processing instruction
E0A00000 , 0DE00000 , 0800100C , ' DATA# , F2100FFF ,
INSTRUCTIOND# sbc \ ARM Assembler, data processing instruction
E0C00000 , 0DE00000 , 0800100C , ' DATA# , F2100FFF ,
INSTRUCTIOND# rsc \ ARM Assembler, data processing instruction
E0E00000 , 0DE00000 , 0800100C , ' DATA# , F2100FFF ,
INSTRUCTIOND# tst \ ARM Assembler, data processing instruction
E1100000 , 0DF0F000 , FF080010 , ' DATA# , F2000FFF ,
INSTRUCTIOND# teq \ ARM Assembler, data processing instruction
E1300000 , 0DF0F000 , FF080010 , ' DATA# , F2000FFF ,
INSTRUCTIOND# cmp \ ARM Assembler, data processing instruction
E1500000 , 0DF0F000 , FF080010 , ' DATA# , F2000FFF ,
INSTRUCTIOND# cmn \ ARM Assembler, data processing instruction
E1700000 , 0DF0F000 , FF080010 , ' DATA# , F2000FFF ,
INSTRUCTIOND# orr \ ARM Assembler, data processing instruction
E1800000 , 0DE00000 , 0800100C , ' DATA# , F2100FFF ,
INSTRUCTIOND# mov \ ARM Assembler, data processing instruction
E1A00000 , 0DEF0000 , FF08000C , ' DATA# , F2100FFF ,
INSTRUCTIOND# bic \ ARM Assembler, data processing instruction
E1C00000 , 0DE00000 , 0800100C , ' DATA# , F2100FFF ,
INSTRUCTIOND# mvn \ ARM Assembler, data processing instruction
E1E00000 , 0DEF0000 , FF08000C , ' DATA# , F2100FFF ,
PUBLIC: s ( -- ) \ ARM Assembler, data processing instruction modifier
00100000 DUP OP-BUILD
;
\ ----------------------------------------------------------------------------
\ Multiply instructions
INSTRUCTIOND mul ( -- ) \ ARM Assembler, multiply instruction
E0000090 , 0FE0F0F0 , FF080010 , F0100000 ,
INSTRUCTIOND mla ( -- ) \ ARM Assembler, multiply instruction
E0200090 , 0FE000F0 , 0C080010 , F0100000 ,
INSTRUCTIOND umull ( -- ) \ ARM Assembler, multiply instruction
E0800090 , 0FE000F0 , 0800100C , F0100000 ,
INSTRUCTIOND umlal ( -- ) \ ARM Assembler, multiply instruction
E0A00090 , 0FE000F0 , 0800100C , F0100000 ,
INSTRUCTIOND smull ( -- ) \ ARM Assembler, multiply instruction
E0C00090 , 0FE000F0 , 0800100C , F0100000 ,
INSTRUCTIOND smlal ( -- ) \ ARM Assembler, multiply instruction
E0E00090 , 0FE000F0 , 0800100C , F0100000 ,
\ ----------------------------------------------------------------------------
\ Load/store instructions
PUBLIC: t ( -- ) \ ARM Assembler, load and store instruction modifier
00200000 01200000 OP-BUILD
;
PUBLIC: bt ( -- ) \ ARM Assembler, load and store instruction modifier
00600000 01600000 OP-BUILD
;
: ADR# ( x -- ) \ Handle immediate operand for ADR pseudo instructions
CODE-ORIGIN @ 8 + -
DUP 0<
IF
NEGATE
OP-VALUE DUP @ 00C00000 XOR SWAP ! \ Turn add into sub
THEN
ARM-DATA-LITERAL
00000FFF
OP-BUILD
;
INSTRUCTION# adr ( -- ) \ ARM Assembler, pseudo op for PC relative address
E28F0000 , 0FFF0000 , FFFFFF0C , ' ADR# ,
: SET-PRE-INDEXING ( x1 -- x2 )
OP-MASK @ 01000000 AND 0=
IF
]-FLAG @ 0=
IF SWAP 01000000 OR SWAP THEN
01000000 OR
THEN
;
: TRY-MEM# ( n -- n | n2 ) \ See if we need a PC relative address
OP-MASK @ 000F000F AND 0= \ if no Rn or index already set...
IF pc CODE-ORIGIN @ 8 + - THEN \ ...use pc relative addressing
;
: MEM# ( n -- ) \ Process immediate operand for LDR/STR instructions
TRY-MEM# \ check for absolute memory address
DUP ABS 0FFF CHECK# \ get abs value and check range
SWAP 0< INVERT 00800000 AND OR \ set U bit if index +ve
02800FFF \ op-mask value
SET-PRE-INDEXING \ set pre-index (P) bit if appropriate
OP-BUILD
RESET-#
;
: MEM-OP-RM ( x1 x2 x3 -- x4 x5 ) \ Process Rm register for LDR/STR ops
\ x1,x2 = op-value,op-mask x3 = Rm register value
\ x4,x5 = modified op-value,op-mask
INVERT 80 AND 10 LSHIFT ROT OR \ set U bit if not -ve register
02000000 OR \ set register index
SWAP 02800000 OR \ add bits to op-mask
SET-PRE-INDEXING \ set pre-index (P) bit if appropriate
;
: MEM-OP ( x -- ) \ Common factor for LDR and STR instructions
0C100000 FF00100C OP-BEGIN
['] MEM# '# !
F3E00FFF OP-DEFAULT !
['] MEM-OP-RM 'RM !
;
PUBLIC: str ( -- ) \ ARM Assembler, store instruction
E5800000 MEM-OP ;
PUBLIC: ldr ( -- ) \ ARM Assembler, load instruction
E5900000 MEM-OP ;
PUBLIC: [ ( -- ) \ ARM Assembler, address bracket
;
PUBLIC: ] ( -- ) \ ARM Assembler, address bracket
TRUE ]-FLAG ! ;
PUBLIC: ! ( -- ) \ ARM Assembler, address write-back modifier
00200000 DUP OP-BUILD ;
: EXTRA-MEM# ( n -- ) \ Handle immediate operand for extra LDR/STR
TRY-MEM# \ check for absolute memory address
DUP ABS 0FF CHECK# \ get abs value and check range
DUP 0F0 AND 4 LSHIFT SWAP 0F AND OR \ covert value into op-code format
00400000 OR \ set I bit
SWAP 0< INVERT 00800000 AND OR \ set U bit if index +ve
00C00F0F \ op-mask value
SET-PRE-INDEXING \ set pre-index bit if appropriate
OP-BUILD
RESET-#
;
: EXTRA-MEM-OP-RM ( x1 x2 x3 -- x4 x5 ) \ Process Rm for extra LDR/STR
\ x1,x2 = op-value,op-mask x3 = Rm register value
\ x4,x5 = modified op-value,op-mask
INVERT 80 AND 10 LSHIFT ROT OR \ set U bit if not -ve register
SWAP 00C00000 OR \ add bits to op-mask
SET-PRE-INDEXING \ set pre-index (P) bit if appropriate
;
: EXTRA-MEM-OP2 ( x -- ) \ Mutate into extra load/store instruction
OP-VALUE @ F0000000 AND OR \ add in condition code
0E1000F0 \ op-mask value
OP-MASK @ F0000000 AND OR \ add in condition code mask
FF00100C OP-INIT \ transmute instruction into new form
F1E00F0F OP-DEFAULT !
['] EXTRA-MEM# '# !
['] EXTRA-MEM-OP-RM 'RM !
;
: EXTRA-MEM-OP ( x -- )
OP-VALUE @ 00100000 AND OR \ add in ldr/str bit
EXTRA-MEM-OP2
;
PUBLIC: h ( -- ) \ ARM Assembler, load and store instruction modifier
01C000B0 EXTRA-MEM-OP ;
PUBLIC: sb ( -- ) \ ARM Assembler, load and store instruction modifier
01C000D0 EXTRA-MEM-OP ;
PUBLIC: sh ( -- ) \ ARM Assembler, load and store instruction modifier
01C000F0 EXTRA-MEM-OP ;
INSTRUCTIOND swp ( -- ) \ ARM Assembler, swap instruction
E1000090 , 0FB00FF0 , FF10000C , F0400000 ,
INSTRUCTIOND stm ( -- ) \ ARM Assembler, store multiple instruction
E8800000 , 0E100000 , FFFFFF10 , F1E0FFFF ,
INSTRUCTIOND ldm ( -- ) \ ARM Assembler, load multiple instruction
E8900000 , 0E100000 , FFFFFF10 , F1E0FFFF ,
: MULTI-TYPE ( x "<spaces>name" -- )
PUBLIC-CREATE ,
DOES> ( -- )
@ 01800000 OP-BUILD
;
00000000 MULTI-TYPE da \ ARM Assembler, load/store multiple modifier
00800000 MULTI-TYPE ia \ ARM Assembler, load/store multiple modifier
01000000 MULTI-TYPE db \ ARM Assembler, load/store multiple modifier
01800000 MULTI-TYPE ib \ ARM Assembler, load/store multiple modifier
PUBLIC: { ( -- ) \ ARM Assembler, load/store multiple register list brace
TRUE {-FLAG ! ;
PUBLIC: } ( -- ) \ ARM Assembler, load/store multiple register list brace
;
PUBLIC: ^ ( -- ) \ ARM Assembler, load/store multiple instruction modifier
00400000 DUP OP-BUILD ;
\ ----------------------------------------------------------------------------
\ Branch instructions...
: ?BAD-BRANCH ( flag -- )
ABORT" ARM Assembler: Bad branch target"
;
: BRANCH# ( x -- ) \ Handle immediate operand for branch instruction
DUP 3 AND ?BAD-BRANCH \ Check target is word aligned
CODE-ORIGIN @ 8 + -
DUP 0< OVER XOR FC000000 AND ?BAD-BRANCH \ Check range for branch
2 RSHIFT 00FFFFFF AND
00FFFFFF OP-BUILD
RESET-#
;
INSTRUCTION# b ( -- )
EA000000 , 0F000000 , FFFFFFFF , ' BRANCH# ,
PUBLIC: b ( -- ) \ ARM Assembler, branch instruction or LDR/STR modifier
OP-MASK @ DUP 0= SWAP 000FF000 AND OR
IF b EXIT THEN \ branch instruction
00400000 DUP OP-BUILD \ byte modifier of load/store instructions
;
INSTRUCTION# bl ( -- ) \ ARM Assembler, branch instruction
EB000000 , 0F000000 , FFFFFFFF , ' BRANCH# ,
INSTRUCTION bx ( -- ) \ ARM Assembler, branch instruction (ARM 4T)
E12FFF10 , 0FFFFFF0 , FFFFFF00 ,
: SWI# ( u -- ) \ Handle immediate operand for SWI instructions
00FFFFFF CHECK#
00FFFFFF OP-BUILD
RESET-#
;
INSTRUCTION# swi ( -- ) \ ARM Assembler, swi instruction
EF000000 , 0F000000 , FFFFFFFF , ' SWI# ,
\ ----------------------------------------------------------------------------
\ MRS and MSR instructions...
INSTRUCTION mrs ( -- ) \ ARM Assembler, status register instruction
E10F0000 , 0FBF0FFF , FFFFFF0C ,
: PSR ( x -- ) \ Common factor for PSR operands
00400000 OP-BUILD
OP-MASK @ 000F0000 AND IF EXIT THEN \ end if mrs instruction
00090000 000F0000 OP-BUILD \ set f and c field mask
;
PUBLIC: cpsr ( -- ) \ ARM Assembler, status register
00000000 PSR ;
PUBLIC: spsr ( -- ) \ ARM Assembler, status register
00400000 PSR ;
INSTRUCTIOND# msr ( -- ) \ ARM Assembler, status register instruction
E120F000 , 0DB0F000 , FFFFFF00 , ' DATA# , F2000FF0 ,
FLAGS PSR-FLAGS \ Parse fields for PSR register
CHAR f C, 13 C,
CHAR s C, 12 C,
CHAR x C, 11 C,
CHAR c C, 10 C,
0 C,
PUBLIC: cpsr_ ( -- ) \ ARM Assembler, status register
00000000 00400000 OP-BUILD PSR-FLAGS ;
PUBLIC: spsr_ ( -- ) \ ARM Assembler, status register
00400000 00400000 OP-BUILD PSR-FLAGS ;
\ ----------------------------------------------------------------------------
\ Coprocessor instructions...
: COPROCESSOR ( u "<spaces>name" -- ) \ Definer for coprocessor
PUBLIC-CREATE , DOES> @ 00000F00 OP-BUILD ;
000 COPROCESSOR p0 \ ARM Assembler, Coprocessor
100 COPROCESSOR p1 \ ARM Assembler, Coprocessor
200 COPROCESSOR p2 \ ARM Assembler, Coprocessor
300 COPROCESSOR p3 \ ARM Assembler, Coprocessor
400 COPROCESSOR p4 \ ARM Assembler, Coprocessor
500 COPROCESSOR p5 \ ARM Assembler, Coprocessor
600 COPROCESSOR p6 \ ARM Assembler, Coprocessor
700 COPROCESSOR p7 \ ARM Assembler, Coprocessor
800 COPROCESSOR p8 \ ARM Assembler, Coprocessor
900 COPROCESSOR p9 \ ARM Assembler, Coprocessor
A00 COPROCESSOR p10 \ ARM Assembler, Coprocessor
B00 COPROCESSOR p11 \ ARM Assembler, Coprocessor
C00 COPROCESSOR p12 \ ARM Assembler, Coprocessor
D00 COPROCESSOR p13 \ ARM Assembler, Coprocessor
E00 COPROCESSOR p14 \ ARM Assembler, Coprocessor
F00 COPROCESSOR p15 \ ARM Assembler, Coprocessor
: CO-MEM# ( x -- ) \ Handle immediate operand for LDC/STC
DUP
{-FLAG @ 0= IF ABS 2 RROTATE THEN
0FF CHECK#
SWAP 0< INVERT IF 00800000 OR THEN
008000FF
]-FLAG @
IF
\ Post index...
{-FLAG @ 0= IF SWAP 00200000 OR SWAP THEN
01200000 OR
THEN
OP-BUILD
RESET-#
;
INSTRUCTIOND# ldc ( -- ) \ ARM Assembler, co-processor instruction
ED900000 , 0E100000 , FFFF102C , ' CO-MEM# , F1E000FF ,
INSTRUCTIOND# stc ( -- ) \ ARM Assembler, co-processor instruction
ED800000 , 0E100000 , FFFF102C , ' CO-MEM# , F1E000FF ,
PUBLIC: l ( -- ) \ ARM Assembler, co-processor instruction modifier
00400000 DUP OP-BUILD ;
: CO-OP2# ( u -- ) \ Handle coprocessor instruction 2nd op-code
7 CHECK#
5 LSHIFT 000000E0 OP-BUILD
RESET-#
;
: CO-DATA# ( u -- ) \ Handler CDP instruction 1st op-code
0F CHECK#
14 LSHIFT 00F00000 OP-BUILD
['] CO-OP2# '# !
;
INSTRUCTION# cdp ( -- ) \ ARM Assembler, co-processor instruction
EE000000 , 0F000010 , FF20302C , ' CO-DATA# ,
: CO-MOV# ( u -- ) \ Handler MCR/MRC instruction 1st op-code
7 CHECK#
15 LSHIFT 00E00000 OP-BUILD
['] CO-OP2# '# !
;
INSTRUCTION# mcr ( -- ) \ ARM Assembler, co-processor instruction
EE000010 , 0F100010 , FF20300C , ' CO-MOV# ,
INSTRUCTION# mrc ( -- ) \ ARM Assembler, co-processor instruction
EE100010 , 0F100010 , FF20300C , ' CO-MOV# ,
\ ----------------------------------------------------------------------------
\ ARM5 instructions
\ ----------------------------------------------------------------------------
: BLX# ( x -- ) \ Handle immediate operand for BLX instruction
0 F000000F OP-BUILD \ check no operands have been added
DUP 2 AND 17 LSHIFT \ get half-word flag
FA000000 OR FF000000 FFFFFFFF OP-INIT \ transmute instruction to long BLX
FFFFFFFD AND \ clear half-word bit in address
BRANCH# \ insert branch address
;
INSTRUCTION# blx ( -- ) \ ARM Assembler, branch instruction
E12FFF30 , 0FFFFFF0 , FFFFFF00 , ' BLX# ,
\ ----------------------------------------------------------------------------
: BKPT# ( u -- ) \ Handle immediate operand for BKPT instruction
0000FFFF CHECK#
DUP 0000FFF0 AND 4 LSHIFT
SWAP 0000000F AND OR
000FFF0F OP-BUILD
RESET-#
;
INSTRUCTION# bkpt ( -- ) \ ARM Assembler, breakpoint instruction
E1200070 , FFF000F0 , FFFFFFFF , ' BKPT# ,
\ ----------------------------------------------------------------------------
INSTRUCTION clz ( -- ) \ ARM Assembler, count leading zeros instruction
E16F0F10 , 0FFF0FF0 , FFFF000C ,
\ ----------------------------------------------------------------------------
INSTRUCTION# mcr2 ( -- ) \ ARM Assembler, co-processor instruction
FE000010 , FF100010 , FF20300C , ' CO-MOV# ,
INSTRUCTION# mrc2 ( -- ) \ ARM Assembler, co-processor instruction
FE100010 , FF100010 , FF20300C , ' CO-MOV# ,
INSTRUCTIOND# ldc2 ( -- ) \ ARM Assembler, co-processor instruction
FD900000 , FE100000 , FFFF102C , ' CO-MEM# , F1E000FF ,
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