24a0启动代码.s

SUAMSUNG ARM S3C24B0 的初始化代码源文件

;=========================================
; NAME: 24A0INIT.S
; DESC: C start up codes
;       Configure memory, ISR ,stacks
;  Initialize C-variables
; HISTORY:
; 2004.01.10 : ver 0.0 for 24A0A
;=========================================

 GET option.a
 GET memcfg.a
 GET 24A0addr.a

;Pre-defined constants
USERMODE    EQU  0x10
FIQMODE     EQU  0x11
IRQMODE     EQU  0x12
SVCMODE     EQU  0x13
ABORTMODE   EQU  0x17
UNDEFMODE   EQU  0x1b
MODEMASK    EQU  0x1f
NOINT       EQU  0xc0

;The location of stacks
UserStack EQU (_STACK_BASEADDRESS-0x3800) 0x13ff_4800- ~ 
SVCStack    EQU (_STACK_BASEADDRESS-0x2800) 0x13ff_5800 ~
UndefStack EQU (_STACK_BASEADDRESS-0x2400) 0x13ff_5c00 ~
AbortStack EQU (_STACK_BASEADDRESS-0x2000) 0x13ff_6000 ~
IRQStack    EQU (_STACK_BASEADDRESS-0x1000) 0x13ff_7000 ~
FIQStack EQU (_STACK_BASEADDRESS-0x0) 0x13ff_8000 ~ 

;Check if tasm.exe(armasm -16 ...@ADS 1.0) is used.
 GBLL    THUMBCODE
 [ {CONFIG} = 16 
THUMBCODE SETL  {TRUE}
     CODE32
     |   
THUMBCODE SETL  {FALSE}
     ]

     MACRO
 MOV_PC_LR
     [ THUMBCODE
            bx lr
     |
            mov pc,lr
     ]
 MEND

     MACRO
 MOVEQ_PC_LR
     [ THUMBCODE
         bxeq lr
     |
            moveq pc,lr
     ]
 MEND

     MACRO
$HandlerLabel HANDLER $HandleLabel

$HandlerLabel
 sub  sp,sp,#4        decrement sp(to store jump address)
 stmfd sp!,{r0}        PUSH the work register to stack(lr does't push because it return to original address)
 ldr     r0,=$HandleLabel;load the address of HandleXXX to r0
 ldr     r0,[r0]         load the contents(service routine start address) of HandleXXX
 str     r0,[sp,#4]      store the contents(ISR) of HandleXXX to stack
 ldmfd   sp!,{r0,pc}     POP the work register and pc(jump to ISR)
 MEND

 IMPORT  |Image$$RO$$Limit|   End of ROM code (=start of ROM data)
 IMPORT  |Image$$RW$$Base|    Base of RAM to initialise
 IMPORT  |Image$$ZI$$Base|    Base and limit of area
 IMPORT  |Image$$ZI$$Limit|   to zero initialise
 
 IMPORT  __main    The main entry of mon program 

 AREA    Init,CODE,READONLY

 ENTRY 

 b ResetHandler handler for Reset  
 b HandlerUndef handler for Undefined mode
 b HandlerSWI handler for SWI interrupt
 b HandlerPabort handler for PAbort
 b HandlerDabort handler for DAbort
 b .  reserved
    b HandlerIRQ handler for IRQ interrupt 
 b HandlerFIQ handler for FIQ interrupt

VECTOR_BRANCH
    ldr pc,=HandlerEINT0_2    0x20
    ldr pc,=HandlerEINT3_6   
    ldr pc,=HandlerEINT7_10          
    ldr pc,=HandlerEINT11_14          
    ldr pc,=HandlerEINT15_18     0x30   
    ldr pc,=HandlerINT_TICK        
    ldr pc,=HandlerINT_DCTQ      
    ldr pc,=HandlerINT_MC          
    ldr pc,=HandlerINT_ME   0x40
    ldr pc,=HandlerINT_KEYPAD          
    ldr pc,=HandlerINT_TIMER0          
    ldr pc,=HandlerINT_TIMER1          
    ldr pc,=HandlerINT_TIMER2  0x50        
    ldr pc,=HandlerINT_TIMER3_4         
    ldr pc,=HandlerINT_LCD_POST         
    ldr pc,=HandlerINT_CAMIF_S         
    ldr pc,=HandlerINT_WDT_BATFLT 0x60
    ldr pc,=HandlerINT_UART0        
    ldr pc,=HandlerINT_CAMIF_C         
    ldr pc,=HandlerINT_MSM         
    ldr pc,=HandlerINT_DMA         0x70
    ldr pc,=HandlerINT_MMC           
    ldr pc,=HandlerINT_SPI0          
    ldr pc,=HandlerINT_UART1          
    ldr pc,=HandlerINT_AC97_NFLASH  0x80
    ldr pc,=HandlerINT_USBD          
    ldr pc,=HandlerINT_USBH  
    ldr pc,=HandlerINT__IIC     
    ldr pc,=HandlerINT_IrDA_MSTICK 0x90   
    ldr pc,=HandlerINT_SPI1           
    ldr pc,=HandlerINT_RTC         
    ldr pc,=HandlerINT_ADC_PENUP_DOWN   0x9c

 LTORG   
 
HandlerFIQ    HANDLER HandleFIQ
HandlerIRQ    HANDLER HandleIRQ
HandlerUndef   HANDLER HandleUndef
HandlerSWI    HANDLER HandleSWI
HandlerDabort   HANDLER HandleDabort
HandlerPabort   HANDLER HandlePabort

HandlerEINT0_2   HANDLER HandleEINT0_2           
HandlerEINT3_6   HANDLER HandleEINT3_6           
HandlerEINT7_10   HANDLER HandleEINT7_10          
HandlerEINT11_14  HANDLER HandleEINT11_14  
HandlerEINT15_18  HANDLER HandleEINT15_18             
HandlerINT_TICK   HANDLER HandleINT_TICK              
HandlerINT_DCTQ   HANDLER HandleINT_DCTQ              
HandlerINT_MC   HANDLER HandleINT_MC          
HandlerINT_ME   HANDLER HandleINT_ME          
HandlerINT_KEYPAD  HANDLER HandleINT_KEYPAD  
HandlerINT_TIMER0  HANDLER HandleINT_TIMER0  
HandlerINT_TIMER1  HANDLER HandleINT_TIMER1  
HandlerINT_TIMER2  HANDLER HandleINT_TIMER2  
HandlerINT_TIMER3_4  HANDLER HandleINT_TIMER3_4         
HandlerINT_LCD_POST  HANDLER HandleINT_LCD_POST         
HandlerINT_CAMIF_S  HANDLER HandleINT_CAMIF_S         
HandlerINT_WDT_BATFLT HANDLER HandleINT_WDT_BATFLT         
HandlerINT_UART0  HANDLER HandleINT_UART0                
HandlerINT_CAMIF_C  HANDLER HandleINT_CAMIF_C         
HandlerINT_MSM   HANDLER HandleINT_MSM                 
HandlerINT_DMA   HANDLER HandleINT_DMA         
HandlerINT_MMC   HANDLER HandleINT_MMC           
HandlerINT_SPI0   HANDLER HandleINT_SPI0          
HandlerINT_UART1  HANDLER HandleINT_UART1  
HandlerINT_AC97_NFLASH  HANDLER HandleINT_AC97_NFLASH      
HandlerINT_USBD    HANDLER HandleINT_USBD                 
HandlerINT_USBH    HANDLER HandleINT_USBH          
HandlerINT__IIC    HANDLER HandleINT__IIC     
HandlerINT_IrDA_MSTICK  HANDLER HandleINT_IrDA_MSTICK         
HandlerINT_SPI1    HANDLER HandleINT_SPI1          
HandlerINT_RTC    HANDLER HandleINT_RTC                 
HandlerINT_ADC_PENUP_DOWN HANDLER HandleINT_ADC_PENUP_DOWN       

IsrIRQ
 sub sp,sp,#4       reserved for PC
 stmfd sp!,{r8-r9}    
 [ VECTOR_MODE
  ldr r9,=VAR
  ldr r8,[r9]
 |
  ldr r9,=INTOFFSET
  ldr r9,[r9]
  ldr r8,=HandleEINT0_2
  add r8,r8,r9,lsl #2
  ldr r8,[r8]
 ]
 str r8,[sp,#8]
 ldmfd sp!,{r8-r9,pc}

;=======
; ENTRY  
;=======
ResetHandler
 ldr r0,=WTCON       watch dog disable 
 ldr r1,=0x0         
 str r1,[r0]

 ldr r0,=INTMSK
 ldr r1,=0xffffffff  all interrupt disable
 str r1,[r0]

 ldr r0,=INTSUBMSK
 ldr r1,=0xffffffff all sub interrupt disable
 str r1,[r0]
 
 ldr r0,=LCDINTMSK
 ldr r1,=0x3   all LCD sub interrupt disable
 str r1,[r0]
 
 To reduce PLL lock time, adjust the LOCKTIME register. 
 ldr r0,=LOCKTIME
 ldr r1,=0xfff0fff
 str r1,[r0]

    [ MPLL_ON_START
  Configure CLKDIVN
  ldr r0,=CLKDIVN          
  ldr r1,=((HCLKdiv<<1)|(PCLKdiv<<0))  
  str r1, [r0]

  Configure MPLL
  ldr r0,=MPLLCON          
  ldr r1,=((M_MDIV<<12)|(M_PDIV<<4)|M_SDIV)  
  str r1,[r0]
 ]

    [ UPLL_ON_START
  Configure UPLL
  ldr r0,=UPLLCON          
  ldr r1,=((U_MDIV<<12)|(U_PDIV<<4)|U_SDIV)  
  str r1,[r0]
 ]

    [ VECTOR_MODE
  Enable Vectored Interrupt Mode
  ldr r0,=VECINTMODE
  ldr r1,=0x1  
  str r1,[r0]
 ]

 Set ROM/SRAM control registers
 ldr r0,=SMRDATA
 ldmia   r0,{r1-r4}
 ldr r0,=SROM_BW
 stmia   r0,{r1-r4}

 Set SDRAM control registers
 ldr r1, =SDRAM_BANKCFG
 ldr r3, =SDRAM_BANKCON
 ldr r5, =SDRAM_REFRESH
 
 1st : issue precharge all command
 mov r0, #0x1
 str r0, [r3]
 
 2nd : make refresh cycle 15clk
 mov r0, #0xf
 str r0, [r5]

 3rd : wait 120clk
 mov r0, #0x100
0 subs r0, r0,#1
 bne %B0 

 4th : set normal operation(133MHz) refresh cycle
 ldr r0, =REFCYC
 str r0, [r5]    

 5th : set cfg/ctrl/timeout registers
 ldr r0, =SDRAM_CFG
 str r0, [r1]
 mov r0, #0x0
 str r0, [r3]    memcon. WB off, normal

 6th : MRS command
 mov r0, #0x2
 str r0, [r3]

 7th : issue EMRS command(only mobile)
 mov r0, #0x3
 str r0, [r4]

 8th : Normal Operation 
 mov r0, #0x0
 str r0, [r3]    memcon. WB off, normal
 
    Initialize stacks
 bl InitStacks
 
    Setup IRQ handler
 ldr r0,=HandleIRQ       This routine is needed
 ldr r1,=IsrIRQ          if there isn't 'subs pc,lr,#4' at 0x18, 0x1c
 str r1,[r0]

 If main() is used, the variable initialization will be done in __main().
    [ :LNOT:USE_MAIN 
     Copy and paste RW data/zero initialized data
  LDR     r0, =|Image$$RO$$Limit|  Get pointer to ROM data
  LDR     r1, =|Image$$RW$$Base|   and RAM copy
  LDR     r3, =|Image$$ZI$$Base|  
  
  Zero init base => top of initialised data
  CMP     r0, r1       Check that they are different
  BEQ     %F2
1       
  CMP     r1, r3       Copy init data
  LDRCC   r2, [r0], #4    --> LDRCC r2, [r0] + ADD r0, r0, #4         
  STRCC   r2, [r1], #4    --> STRCC r2, [r1] + ADD r1, r1, #4
  BCC     %B1
2       
  LDR     r1, =|Image$$ZI$$Limit|  Top of zero init segment
  MOV     r2, #0
3       
  CMP     r3, r1       Zero init
  STRCC   r2, [r3], #4
  BCC     %B3
    ]

    GBLS MAIN
    [ USE_MAIN
     IMPORT __main
MAIN SETS "__main"
    |
 IMPORT  CEntry    
MAIN  SETS "CEntry"
    ]    
 

    [ :LNOT:THUMBCODE
     bl $MAIN        Don't use main() because ......
     b .                       
    ]

    [ THUMBCODE         for start-up code for Thumb mode
     orr lr,pc,#1
     bx lr
     CODE16
     bl $MAIN        Don't use main() because ......
     b .
     CODE32
    ]


;function initializing stacks
InitStacks
 Don't use DRAM,such as stmfd,ldmfd......
 SVCstack is initialized before
 Under toolkit ver 2.5, 'msr cpsr,r1' can be used instead of 'msr cpsr_cxsf,r1'
 mrs r0,cpsr
 bic r0,r0,#MODEMASK
 orr r1,r0,#UNDEFMODE|NOINT
 msr cpsr_cxsf,r1  UndefMode
 ldr sp,=UndefStack
 
 orr r1,r0,#ABORTMODE|NOINT
 msr cpsr_cxsf,r1  AbortMode
 ldr sp,=AbortStack

 orr r1,r0,#IRQMODE|NOINT
 msr cpsr_cxsf,r1  IRQMode
 ldr sp,=IRQStack
    
 orr r1,r0,#FIQMODE|NOINT
 msr cpsr_cxsf,r1  FIQMode
 ldr sp,=FIQStack

 bic r0,r0,#MODEMASK|NOINT
 orr r1,r0,#SVCMODE
 msr cpsr_cxsf,r1  SVCMode
 ldr sp,=SVCStack
 
 USER mode has not be initialized.
 
 mov pc,lr 
 The LR register won't be valid if the current mode is not SVC mode.
 

 LTORG

SMRDATA DATA
; Memory configuration should be optimized for best performance 
; The following parameter is not optimized.                     
; Memory access cycle parameter strategy
; 1) The memory settings is safe parameters even at HCLK=50Mhz.
; 2) SDRAM refresh period is for HCLK=50Mhz. 

 DCD ((B2_CS<<9)|(B2_BWSCON<<6)|(B1_BWSCON<<3)|0)
    DCD ((B0_Tacs<<14)|(B0_Tcos<<12)|(B0_Tacc<<8)|(B0_Tcoh<<6)|(B0_Tcah<<4)|(B0_Tacp<<2)|(B0_PMC))   GCS0
    DCD ((B1_Tacs<<14)|(B1_Tcos<<12)|(B1_Tacc<<8)|(B1_Tcoh<<6)|(B1_Tcah<<4)|(B1_Tacp<<2)|(B1_PMC))   GCS1 
    DCD ((B2_Tacs<<14)|(B2_Tcos<<12)|(B2_Tacc<<8)|(B2_Tcoh<<6)|(B2_Tcah<<4)|(B2_Tacp<<2)|(B2_PMC))   GCS2

     ALIGN


     AREA RamData, DATA, READWRITE

        ^   _ISR_STARTADDRESS
HandleReset    #   4
HandleUndef    #   4
HandleSWI      #   4
HandlePabort      #   4
HandleDabort      #   4
HandleReserved    #   4
HandleIRQ      #   4
HandleFIQ      #   4

;Don't use the label 'IntVectorTable',
;The value of IntVectorTable is different with the address you think it may be.
;IntVectorTable
HandleEINT0_2    #   4
HandleEINT3_6    #   4
HandleEINT7_10   #   4
HandleEINT11_14   #   4
HandleEINT15_18      #   4
HandleINT_TICK       #   4
HandleINT_DCTQ       #   4
HandleINT_MC   #   4
HandleINT_ME   #   4
HandleINT_KEYPAD  #   4
HandleINT_TIMER0  #   4
HandleINT_TIMER1  #   4
HandleINT_TIMER2  #   4
HandleINT_TIMER3_4  #   4
HandleINT_LCD_POST  #   4
HandleINT_CAMIF_S  #   4
HandleINT_WDT_BATFLT #   4
HandleINT_UART0         #   4
HandleINT_CAMIF_C  #   4
HandleINT_MSM         #   4
HandleINT_DMA        #   4
HandleINT_MMC        #   4
HandleINT_SPI0   #   4
HandleINT_UART1   #   4
HandleINT_AC97_NFLASH   #   4
HandleINT_USBD         #   4
HandleINT_USBH   #   4
HandleINT__IIC     #   4
HandleINT_IrDA_MSTICK #   4
HandleINT_SPI1          #   4
HandleINT_RTC         #   4
HandleINT_ADC_PENUP_DOWN #   4

        END