cache.c

日本著名的的嵌入式实时操作系统T-Kernel的源码及用户手册。

/*
 *----------------------------------------------------------------------
 *    T-Kernel
 *
 *    Copyright (C) 2004 by Ken Sakamura. All rights reserved.
 *    T-Kernel is distributed under the T-License.
 *----------------------------------------------------------------------
 *
 *    Version:   1.01.00
 *    Released by T-Engine Forum(http://www.t-engine.org) at 2004/6/28.
 *
 *----------------------------------------------------------------------
 */

/*
 *	cache.c (SH7751R)
 *	Cache Operation
 */

#include <basic.h>
#include <tk/tkernel.h>
#include <tk/sysdef.h>

#define	PAGESIZE	0x1000		/* Page size*/
#define	CACHE_LINESZ	0x20		/* Chache line size */

#define	ICACHE_ADR_TOP	0xf0000000	/* Instruction cache address array */
#define	ICACHE_DAT_TOP	0xf1000000	/* Instruction cache data array */
#define	ICACHE_WAY_MSK	0x00002000
#define	ICACHE_ENT_MSK	0x00001fe0

#define	DCACHE_ADR_TOP	0xf4000000	/* Data cache address array */
#define	DCACHE_DAT_TOP	0xf5000000	/* Data cache data array */
#define	DCACHE_WAY_MSK	0x00004000
#define	DCACHE_ENT_MSK	0x00003fe0

#define	CACHE_V		0x00000001	/* Valid */
#define	CACHE_U		0x00000002	/* Dirty */
#define	CACHE_TAG	0xfffffc00	/* Tag */

#define	CACHE_A		0x00000008	/* Associative specification */

/*
 *  One page cache flush
 *	Flush one page cache (4KB) corresponding to logical address 'laddr'.
 *	'laddr' must be top address of page.
 *	
 *	Cache control program must be located at non-cached area,
 *	so P2 area (as shadow area) is used to execute the program.
 *	For this purpose, call the program with address pointed by
 *	'_FlushCache_', and don't call '_flush_cache_' directly.
 */
LOCAL void _flush_cache_( UW laddr )
{
	UW	icarray, ent;

	ent = laddr;
	if ( (in_w(CCR) & CCR_IIX) != 0 ) ent >>= 25 - 12;
	ent &= ICACHE_ENT_MSK & ~(PAGESIZE-1);

	icarray = ICACHE_ADR_TOP | CACHE_A | ent;

	for ( ent = 0; ent < PAGESIZE; ent += CACHE_LINESZ ) {
		/* Instruction cache */
		*(UW*)(icarray + ent) = (laddr + ent) & CACHE_TAG;

		/* Data cache */
		Asm("ocbp @%0":: "r"(laddr + ent));
	}
}

LOCAL FP _FlushCacheP2_ = (FP)((UW)&_flush_cache_ + 0x20000000);

#define	FlushCacheP2(laddr)	(*_FlushCacheP2_)(laddr)

/*
 * Cache flush
 *	Flush cache between 'laddr' and 'len' bytes areas.
 *	Writeback and disable cache
 */
EXPORT void FlushCache( VP laddr, INT len )
{
	UW	top, end;
	UINT	imask;

	top = (UW)laddr & ~(PAGESIZE-1);
	end = (UW)laddr + len;

	while ( top < end ) {

		DI(imask);
		FlushCacheP2(top);
		EI(imask);

		top += PAGESIZE;
	}
}