cache_asm.s

日本著名的的嵌入式实时操作系统T-Kernel的源码及用户手册。

/*
 *----------------------------------------------------------------------
 *    T-Kernel
 *
 *    Copyright (C) 2004 by Ken Sakamura. All rights reserved.
 *    T-Kernel is distributed under the T-License.
 *----------------------------------------------------------------------
 *
 *    Version:   1.01.00
 *    Released by T-Engine Forum(http://www.t-engine.org) at 2004/6/28.
 *
 *----------------------------------------------------------------------
 */

/*
 *	cache_asm.S (VR4131)
 *	Cache Flush
 */

#define _in_asm_source_
#include <machine.h>
#include <tk/asm.h>
#include "cache_asm.h"

.macro mtc0_PSR reg
	mtc0	\reg, $CP0_PSR
.endm

/* ------------------------------------------------------------------------ */

/*
 * Flush memory cache (Both instruction/data cache)
 *	void FlushCacheOneBlock( VP laddr )
 */
	.text
	.balign	4
	.globl	Csym(FlushCacheOneBlock)
	.type	Csym(FlushCacheOneBlock), %function
Csym(FlushCacheOneBlock):
	mfc0	$t7, $CP0_PSR			// t7 = PSR save
	and	$t0, $t7, ~SR_IE
	mtc0	$t0, $CP0_PSR			// Interrupt disable IE=0
	NOP(HzD_MTC0 - HzS_INT - 1)
	nop

	and	$a0, $a0, ~(CACHE_BLOCK_SIZE-1)	// Head of 'laddr' page
	addu	$t1, $a0, CACHE_BLOCK_SIZE	// t1 = End address

	move	$t0, $a0			// Flush instruction cache
	lw	$t2, Csym(ICacheLineSize)
  lc_1:
	cache	(4 << 2)|0, ($t0)		// Hit Invalidate (instruction)
	addu	$t0, $t2
	bltu	$t0, $t1, lc_1

	move	$t0, $a0			// Flush data cache
	lw	$t2, Csym(DCacheLineSize)
  lc_2:
	cache	(5 << 2)|1, ($t0)		// Hit Write Back Invalidate (Data)
	addu	$t0, $t2
	bltu	$t0, $t1, lc_2

	mtc0_PSR $t7				// Return interrupt disable state
	jr	$ra