cpu_insn.h

日本著名的的嵌入式实时操作系统T-Kernel的源码及用户手册。

/*
 *----------------------------------------------------------------------
 *    T-Kernel
 *
 *    Copyright (C) 2004 by Ken Sakamura. All rights reserved.
 *    T-Kernel is distributed under the T-License.
 *----------------------------------------------------------------------
 *
 *    Version:   1.01.00
 *    Released by T-Engine Forum(http://www.t-engine.org) at 2004/6/28.
 *
 *----------------------------------------------------------------------
 */

/*
 *	cpu_insn.h (VR4131)
 *	CPU-Dependant Operation
 */

#ifndef _CPU_INSN_
#define _CPU_INSN_

#include <sys/sysinfo.h>

/*
 * 32 bits -> 64 bits conversion
 */
Inline void SetDW( DW *dw, INT x )
{
	*(long long*)dw = x;
}

/* ------------------------------------------------------------------------ */
/*
 *	Control register operation
 */

/*
 * Get CP0 status register (PSR)
 */
Inline UINT getPSR( void )
{
	UINT	psr;
	Asm("mfc0 %0, $12": "=r"(psr));
	return psr;
}

/* ------------------------------------------------------------------------ */
/*
 *	EIT-related
 */

/*
 * Monitor use vector number
 */
#define	VECNO_DEFAULT	EIT_DEFAULT	/* Default handler */
#define	VECNO_INTERRUPT	EIT_EXC(0)	/* Interrupt branch processing */
#define	VECNO_SYSCALL	EIT_EXC(8)	/* System call branch processing */
#define	VECNO_WATCH	EIT_EXC(23)	/* Watch point */
#define	VECNO_MONITOR	( 37 )		/* Monitor service call */
#define	VECNO_BREAK	( 42 )		/* Break point */
#define	VECNO_IP2	EIT_IP(2)	/* Interrupt controller branch processing */
#define	VECNO_GPIO	EIT_IRQ(8)	/* GPIO interrupt branch processing */
#define	VECNO_FPGA	EIT_GPIO(0)	/* FPGA Interrupt branch processing */

/*
 * For saving monitor exception handler
 */
typedef struct monhdr {
	FP	default_hdr;		/* Default handler */
	FP	interrupt_hdr;		/* Interrupt branch processing */
	FP	syscall_hdr;		/* System call branch processing */
	FP	watch_hdr;		/* Watch point */
	FP	monitor_hdr;		/* Monitor service call */
	FP	break_hdr;		/* Break point */
	FP	ip2_hdr;		/* Interrupt controller interrupt
					   branch processing */
	FP	gpio_hdr;		/* GPIO interrupt branch processing */
	FP	fpga_hdr;		/* FPGA Interrupt branch processing */
} MONHDR;

/* For saving monitor exception handler */
IMPORT MONHDR	SaveMonHdr;

/*
 * Set interrupt handler
 */
Inline void define_inthdr( INT vecno, FP inthdr )
{
	SCArea->intvec[vecno] = inthdr;

	/* Writeback cache */
	Asm("cache (6 << 2)|1, (%0)":: "r"(&SCArea->intvec[vecno]));
}

IMPORT	VP	int_stack_top;	/* Exception stack top */

/*
 * If it is the task-independent part, TRUE
 */
Inline BOOL isTaskIndependent( void )
{
	return ( SCInfo.istkpos < int_stack_top )? TRUE: FALSE;
}

/*
 * Move to/Restore task independent part
 */
Inline void EnterTaskIndependent( void )
{
	((DW*)SCInfo.istkpos) -= 2;
}
Inline void LeaveTaskIndependent( void )
{
	((DW*)SCInfo.istkpos) += 2;
}

/*
 * If dispatch disable, TRUE
 */
Inline BOOL isDispatchDisabled( void )
{
	return ( (getPSR() & SR_IM(1)) == 0 )? TRUE: FALSE;
}

/* ------------------------------------------------------------------------ */
#endif /* _CPU_INSN_ */