📄 cache.c
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/* *---------------------------------------------------------------------- * T-Kernel * * Copyright (C) 2004 by Ken Sakamura. All rights reserved. * T-Kernel is distributed under the T-License. *---------------------------------------------------------------------- * * Version: 1.01.00 * Released by T-Engine Forum(http://www.t-engine.org) at 2004/6/28. * *---------------------------------------------------------------------- *//* * cache.c (MC9328) * Cache Operation */#include <basic.h>#include <tk/tkernel.h>/* * Flush the whole memory cache * Need to flush cache every time mapping of the logical address and * the physical address changes because this cache is identified by the * logical address(Cache coherency is not guaranteed on hardware). */EXPORT void FlushCache( VP laddr, INT len ){ UINT index, seg; /* Invalidate instruction cache */ Asm("mcr p15, 0, %0, cr7, c5, 0":: "r"(0)); /* Write back and invalidate data cache */ for ( index = 0; index < 64; index++ ) { for ( seg = 0; seg < 8; seg++ ) { Asm("mcr p15, 0, %0, cr7, c14, 2" :: "r"((index << 26) | (seg << 5))); } }}
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