tkdev_timer.h

日本著名的的嵌入式实时操作系统T-Kernel的源码及用户手册。

/*
 *----------------------------------------------------------------------
 *    T-Kernel
 *
 *    Copyright (C) 2004 by Ken Sakamura. All rights reserved.
 *    T-Kernel is distributed under the T-License.
 *----------------------------------------------------------------------
 *
 *    Version:   1.01.00
 *    Released by T-Engine Forum(http://www.t-engine.org) at 2004/6/28.
 *
 *----------------------------------------------------------------------
 */

/*
 *	tkdev_timer.h (S1C38K)
 *	Hardware-Dependent Timer Processing
 */

#ifndef _TKDEV_TIMER_
#define	_TKDEV_TIMER_

#include <tk/syslib.h>
#include <sys/sysinfo.h>
#include "tkdev_conf.h"

/*
 * Settable interval range (millisecond)
 */
#define	MIN_TIMER_PERIOD	1
#define	MAX_TIMER_PERIOD	50

IMPORT UW	TimerClkDiv;	/* Dividing rate of timer clock */

/*
 * Set timer
 */
Inline void init_hw_timer( void )
{
	UW	n, mod, imask;

	/* Determine dividing rate */
	n = (UW)TIMER_PERIOD * (TMCLK * 1000) / 65536;
	mod = ( n <  4 )? (TimerClkDiv =  4, TMC_DIV4 ):  /*  4 dividing */
	      ( n <  8 )? (TimerClkDiv =  8, TMC_DIV8 ):  /*  8 dividing */
	      ( n < 16 )? (TimerClkDiv = 16, TMC_DIV16):  /* 16 dividing */
			  (TimerClkDiv = 32, TMC_DIV32);  /* 32 dividing */
	mod |= TMC_CYC|TMC_RELOAD;

	DI(imask);

	/* Select timer */
	out_w(TM_SEL, TM_SEL1);

	/* Set timer mode/Stop timer */
	out_w(TM1_CTRL, mod);
	out_w(TM1_INTCLR, 0); /* Interrupt clear */

	/* Set counter */
	n = (UW)TIMER_PERIOD * (TMCLK * 1000) / TimerClkDiv - 1;
	out_w(TM1_LOAD, n);

	/* Start timer count */
	out_w(TM1_CTRL, mod | TMC_ENA);

	EI(imask);
}

/*
 * Timer start processing
 *	Initialize the timer and start the periodical timer interrupt.
 */
Inline void start_hw_timer( void )
{
IMPORT	void	timer_handler_startup( void );

	/* Set timer */
	init_hw_timer();

	/* Interrupt handler definition */
	define_inthdr(VECNO_TM1, timer_handler_startup);

	/* Timer interrupt enable */
	SetIntMode(VECNO_TM1, IM_LEVEL|IM_HI);
	EnableInt(VECNO_TM1);
}

/*
 * Clear timer interrupt
 *	Clear the timer interrupt request. Depending on the type of
 *	hardware, there are two timings for clearing: at the beginning
 *	and the end of the interrupt handler.
 *	'clear_hw_timer_interrupt()' is called at the beginning of the
 *	timer interrupt handler.
 *	'end_of_hw_timer_interrupt()' is called at the end of the timer
 *	interrupt handler.
 *	Use either or both according to hardware.
 */
Inline void clear_hw_timer_interrupt( void )
{
	/* Enter on interrupt enable state */

	/* Disable its own interrupt to enable a multiplexed interrupt */
	out_w(IRQ_DIS, 1 << TM1_IRQ);

	/* Clear timer interrupt */
	out_w(TM_SEL, TM_SEL1);  /* Select timer */
	out_w(TM1_INTCLR, 0);

	/* Multiplexed interrupt enable */
	Asm("msr cpsr_c, %0":: "i"(PSR_SVC));
}
Inline void end_of_hw_timer_interrupt( void )
{
	/* Interrupt disable */
	Asm("msr cpsr_c, %0":: "i"(PSR_SVC|PSR_DI));

	/* Enable its own interrupt */
	out_w(IRQ_ENA, 1 << TM1_IRQ);
}

/*
 * Timer stop processing
 *	Stop the timer operation.
 *	Called when system stops.
 */
Inline void terminate_hw_timer( void )
{
	/* Timer interrupt disable */
	DisableInt(VECNO_TM1);
}

/*
 * Get processing time from the previous timer interrupt to the
 * current (nanosecond)
 *	Consider the possibility that the timer interrupt occurred
 *	during the interrupt disable and calculate the processing time
 *	within the following
 *	range: 0 <= Processing time < TIMER_PERIOD * 2
 */
Inline UINT get_hw_timer_nsec( void )
{
	UW	ofs, max, unf, imask;

	DI(imask);

	out_w(TM_SEL, TM_SEL1);  /* Select timer */

	max = (in_w(TM1_LOAD) & 0xffff) + 1;
	do {
		unf = in_w(TM1_CTRL) & TMC_INT;
		ofs = max - (in_w(TM1_COUNT) & 0xffff);
	} while ( unf != (in_w(TM1_CTRL) & TMC_INT) );
	if ( unf != 0 ) ofs += max;

	EI(imask);

	return ofs * (1000 * TimerClkDiv) / TMCLK;
}

#endif /* _TKDEV_TIMER_ */