syslib_depend.h

日本著名的的嵌入式实时操作系统T-Kernel的源码及用户手册。

/*
 *----------------------------------------------------------------------
 *    T-Kernel
 *
 *    Copyright (C) 2004 by Ken Sakamura. All rights reserved.
 *    T-Kernel is distributed under the T-License.
 *----------------------------------------------------------------------
 *
 *    Version:   1.01.00
 *    Released by T-Engine Forum(http://www.t-engine.org) at 2004/6/28.
 *
 *----------------------------------------------------------------------
 */

/*
 *	@(#)syslib_depend.h (tk/MC9328)
 *
 *	T-Kernel/SM MC9328 Library
 */

#ifndef __TK_SYSLIB_DEPEND_H__
#define __TK_SYSLIB_DEPEND_H__

#include <tk/errno.h>

#ifdef __cplusplus
extern "C" {
#endif

/*
 * CPU interrupt control
 *	'intsts' is the value of CPSR in CPU
 *	disint()  Set CPSR.I = 1 and return the original CPSR
 *		  to the return value.
 *	enaint()  Set CPSR.I = intsts.I. Do not change except
 *		  for CPSR.I.
 *		  Return the original CPSR to the return value.
 */
IMPORT UINT disint( void );
IMPORT UINT enaint( UINT intsts );
#define	DI(intsts)	( (intsts) = disint() )
#define	EI(intsts)	( enaint(intsts) )
#define	isDI(intsts)	( ((intsts) & 0x00c0) != 0 )

/*
 * Interrupt vector
 *	The interrupt vector is the index number of the vector table.
 */
typedef UINT	INTVEC;

/* Convert to interrupt definition number */
#define	DINTNO(intvec)	(intvec)

/*
 * Interrupt vector value (part)
 */
#define	IV_IRQ(n)	(  32 + (n) )	/* IRQ			0 - 63 */
#define	IV_GPA(n)	(  96 + (n) )	/* GPIO Port A 		0 - 31 */
#define	IV_GPB(n)	( 128 + (n) )	/* GPIO Port B 		0 - 31 */
#define	IV_GPC(n)	( 160 + (n) )	/* GPIO Port C 		0 - 31 */
#define	IV_GPD(n)	( 192 + (n) )	/* GPIO Port D 		0 - 31 */
#define	IV_FPGA1(n)	( 224 + (n) )	/* FPGA IRQ_STR1	0 - 7  */
#define	IV_FPGA2(n)	( 232 + (n) )	/* FPGA IRQ_STR2	0 - 7  */
#define	IV_EXBOARD	( 240 )		/* Extension board	       */

/*
 * Interrupt controller operation
 *	Operation functions of interrupt controller support IRQ, GPIO, FPGA
 *	interrupts. Some functions treat part of those interrupts.
 *	FIQ interrupt is specified by IRQ interrupt vector which means the
 *	same factor. If invalid vector is specified, operation is not
 *	guaranteed.
 */

/*
 * Set interrupt enable level
 *	Disable IRQ interrupts which level is less then or equal to specified
 *	'level'. 'level' must be '-1'-'15'.
 *	If '-1' is specified, all level IRQ interrupts are enable.
 *	If '15' is specified, all level IRQ interrupts are disable.
 *	'level' is set to the NIMASK register of interrupt controller.
 *	Initial value is '-1'.
 *	This function returns the interrupt enable level before being changed.
 */
IMPORT INT SetIntLevel( INT level );

/*
 * Set interrupt mode
 *	Set accept mode to 'mode' regarding interrupt specified by 'intvec'.
 *	If 'mode' is not correct value, operation is not guaranteed.
 *
 *	For IRQ,  mode := (IM_IRQ || IM_FIQ)
 *	Set the INTTYPE register of interrupt controller.
 *	Initial value is IM_IRQ.
 *
 *	For GPIO, mode := (IM_LEVEL || IM_EDGE) | (IM_HI || IM_LOW)
 *	Set the ICR register of interrupt controller.
 *
 *	For FPGA interrupt, cannot set.
 */
IMPORT void SetIntMode( INTVEC intvec, UINT mode );

#define	IM_IRQ		0x00	/* IRQ interrupt */
#define	IM_FIQ		0x10	/* FIQ interrupt */
#define	IM_LEVEL	0x02	/* level trigger */
#define	IM_EDGE		0x00	/* edge trigger */
#define	IM_HI		0x00	/* high level trigger/positive edge trigger */
#define	IM_LOW		0x01	/* low level trigger/negagive edge trigger */

/*
 * Enable interrupt
 *	Enable interrupt specified by 'intvec'.
 *
 *	For IRQ, level := '0'-'15'.
 *	level=0 means lowest priority level, level=15 means highest.
 *	If 'level' is outside this range, operation is not guaranteed.
 *	Set the NIPRIORITY register with the value 'level' and set
 *	interrupt enable to the INTENABLE register.
 *	For FIQ, 'level' has no mean.
 *
 *	For GPIO, 'level' is ignored.
 *	Set the IMR register of GPIO controller to interrupt enable.
 *
 *	For FPGA, 'level' is ignored.
 *	Set the IRQ_MASK register to interrupt enable.
 */
IMPORT void EnableInt( INTVEC intvec, INT level );

/*
 * Disable interrupt
 *	Disable interrupt specified by 'intvec'.
 *
 *	For IRQ, set the INTENABLE register to interrupt disable state.
 *
 *	For GPIO, set the IMR register to interrupt disable.
 *
 *	For FPGA, set the IRQ_MASK register to interrupt disable.
 */
IMPORT void DisableInt( INTVEC intvec );

/*
 * Clear interrupt request
 *	Clear interrupt request specified by 'intvec'.
 *	This function is valid for GPIO and FPGA interrupts.
 *	For FPGA interrupt, clear 'GPIO Port A pin 7' which connected to FPGA.
 */
IMPORT void ClearInt( INTVEC intvec );

/*
 * Check for existence of interrupt request
 *	Check whether there is an interrupt request specified by 'intvec.'
 *	If there is an interrupt request, return TRUE (except 0).
 */
IMPORT BOOL CheckInt( INTVEC intvec );

/*
 * Issue EOI(End Of Interrupt)
 */
#define	EndOfInt(intvec)

/* ------------------------------------------------------------------------ */

/*
 * I/O port access
 *	Only memory mapped I/O for Arm
 */
Inline void out_w( INT port, UW data )
{
	*(_UW*)port = data;
}
Inline void out_h( INT port, UH data )
{
	*(_UH*)port = data;
}
Inline void out_b( INT port, UB data )
{
	*(_UB*)port = data;
}

Inline UW in_w( INT port )
{
	return *(_UW*)port;
}
Inline UH in_h( INT port )
{
	return *(_UH*)port;
}
Inline UB in_b( INT port )
{
	return *(_UB*)port;
}

#ifdef __cplusplus
}
#endif
#endif /* __TK_SYSLIB_DEPEND_H__ */