syslib_depend.h

日本著名的的嵌入式实时操作系统T-Kernel的源码及用户手册。

/*
 *----------------------------------------------------------------------
 *    T-Kernel
 *
 *    Copyright (C) 2004 by Ken Sakamura. All rights reserved.
 *    T-Kernel is distributed under the T-License.
 *----------------------------------------------------------------------
 *
 *    Version:   1.01.00
 *    Released by T-Engine Forum(http://www.t-engine.org) at 2004/6/28.
 *
 *----------------------------------------------------------------------
 */

/*
 *	@(#)syslib_depend.h (tk/S1C38K)
 *
 *	T-Kernel/SM S1C38000 Library
 */

#ifndef __TK_SYSLIB_DEPEND_H__
#define __TK_SYSLIB_DEPEND_H__

#include <tk/errno.h>

#ifdef __cplusplus
extern "C" {
#endif

/*
 * CPU interrupt control
 *	'intsts' is the value of CPSR in CPU
 *	disint()  Set CPSR.I = 1 and F = 1 and return the original CPSR
 *		  to the return value.
 *	enaint()  Set CPSR.I,F = intsts.I,F. Do not change except
 *		  for CPSR.I,F.
 *		  Return the original CPSR to the return value.
 */
IMPORT UINT disint( void );
IMPORT UINT enaint( UINT intsts );
#define	DI(intsts)	( (intsts) = disint() )
#define	EI(intsts)	( enaint(intsts) )
#define	isDI(intsts)	( ((intsts) & 0x00c0) != 0 )

/*
 * Interrupt vector
 *	The interrupt vector is the index number of the vector table.
 */
typedef UINT	INTVEC;

/* Convert to interrupt definition number */
#define	DINTNO(intvec)	(intvec)

/*
 * Interrupt vector value (part)
 */
#define	IV_FIQ(n)	( 30 + (n) )	/* Fast interrupt  0-1  */
#define	IV_IRQ(n)	( 32 + (n) )	/* Interrupt  0-31 */
#define	IV_GPA(n)	( 64 + (n) )	/* GPIO Port A interrupt  0-7  */
#define	IV_GPB(n)	( 72 + (n) )	/* GPIO Port B interrupt  0-7  */
#define	IV_FPGA1(n)	( 80 + (n) )	/* FPGA IRQ_STR1 interrupt  0-7  */
#define	IV_FPGA2(n)	( 88 + (n) )	/* FPGA IRQ_STR2 interrupt  0-7  */

/*
 * Interrupt controller control
 *	Available range specified by 'intvec'
 *	EnableInt/DisableInt/CheckInt	FIQ IRQ GPA GPB FPGA1 FPGA2
 *	Others				FIQ IRQ GPA GPB
 *	If any others above are specified, the operation can not be
 *	guaranteed.
 */

/*
 * Interrupt mode setting
 *	Set the interrupt specified by 'intvec' to the mode specified
 *	by 'mode.'
 *	For FIQ IRQ, the interrupt controllers, Level register and
 *	Polarity register, are set.
 *	
 *	For GPA GPB, the GPIO controllers, Interrupt Type register
 *	and Interrupt Polarity register, are set.
 *
 *	mode := (IM_LEVEL || IM_EDGE) | (IM_HI || IM_LOW)
 */
IMPORT void SetIntMode( INTVEC intvec, UINT mode );

#define	IM_LEVEL	0	/* level trigger */
#define	IM_EDGE		1	/* edge  trigger */
#define	IM_HI		2	/* high level trigger/positive edge trigger */
#define	IM_LOW		0	/* low  level trigger/negagive edge trigger */

/*
 * Interrupt enable
 *	Enable the interrupt specified by 'intvec.'
 */
IMPORT void EnableInt( INTVEC intvec );

/*
 * Interrupt disable
 *	Disable the interrupt specified by 'intvec.'
 */
IMPORT void DisableInt( INTVEC intvec );

/*
 * Clear interrupt request
 *	Clear the interrupt request specified by 'intvec.'
 *	Available only for edge trigger.
 *	For edge trigger, need to clear the interrupt with
 *	interrupt handler.
 */
IMPORT void ClearInt( INTVEC intvec );

/*
 * Check for existence of interrupt request
 *	Check whether there is an interrupt request specified by 'intvec.'
 *	If there is an interrupt request, return TRUE (except 0).
 */
IMPORT BOOL CheckInt( INTVEC intvec );

/*
 * Issue EOI(End Of Interrupt)
 */
#define	EndOfInt(intvec)

/* ------------------------------------------------------------------------ */

/*
 * I/O port access
 *	Only memory mapped I/O for Arm
 */
Inline void out_w( INT port, UW data )
{
	*(_UW*)port = data;
}
Inline void out_h( INT port, UH data )
{
	*(_UH*)port = data;
}
Inline void out_b( INT port, UB data )
{
	*(_UB*)port = data;
}

Inline UW in_w( INT port )
{
	return *(_UW*)port;
}
Inline UH in_h( INT port )
{
	return *(_UH*)port;
}
Inline UB in_b( INT port )
{
	return *(_UB*)port;
}

#ifdef __cplusplus
}
#endif
#endif /* __TK_SYSLIB_DEPEND_H__ */