sysdef_depend.h

日本著名的的嵌入式实时操作系统T-Kernel的源码及用户手册。

/*
 *----------------------------------------------------------------------
 *    T-Kernel
 *
 *    Copyright (C) 2004 by Ken Sakamura. All rights reserved.
 *    T-Kernel is distributed under the T-License.
 *----------------------------------------------------------------------
 *
 *    Version:   1.01.00
 *    Released by T-Engine Forum(http://www.t-engine.org) at 2004/6/28.
 *
 *----------------------------------------------------------------------
 */

/*
 *	@(#)sysdef_depend.h (tk/S1C38K)
 *
 *	Definition about S1C38000
 *
 *	Included also from assembler program.
 */

#ifndef __TK_SYSDEF_DEPEND_H__
#define __TK_SYSDEF_DEPEND_H__

/*
 * Program status register (PSR)
 */
#define	PSR_N		0x80000000	/* Condition flag Negative */
#define	PSR_Z		0x40000000	/* Zero */
#define	PSR_C		0x20000000	/* Carry */
#define	PSR_V		0x10000000	/* Overflow */

#define	PSR_I		0x00000080	/* Interrupt (IRQ) disable */
#define	PSR_F		0x00000040	/* Fast Interrupt (FIQ) disable */
#define	PSR_T		0x00000020	/* Thumb mode */

#define PSR_DI		(PSR_I | PSR_F)	/* All Interrupts disable */

#define	PSR_M(n)	( n )		/* Processor mode 0-31 */
#define	PSR_USR		PSR_M(16)	/* User mode */
#define	PSR_FIQ		PSR_M(17)	/* Fast Interrupt (FIQ) mode */
#define	PSR_IRQ		PSR_M(18)	/* Interrupt (IRQ) mode */
#define	PSR_SVC		PSR_M(19)	/* Supervisor mode */
#define	PSR_ABT		PSR_M(23)	/* Abort mode */
#define	PSR_UND		PSR_M(27)	/* Undefined order mode */
#define	PSR_SYS		PSR_M(31)	/* System mode */

/*
 * Task mode flag
 *	System shared information 'taskmode' 
 */
#define	TMF_CPL(n)	( (n) )		/* Current protection level(0-3) */
#define	TMF_PPL(n)	( (n) << 16 )	/* Previous protection level(0-3) */

/*
 * System control coprocessor (CP15): Control register (CR1)
 */
#define	CR1_M	0x0001	/* MMU enable */
#define	CR1_A	0x0002	/* Alignment check enable */
#define	CR1_C	0x0004	/* Cache enable */
#define	CR1_W	0x0008	/* Write buffer enable */
#define	CR1_B	0x0080	/* Endian (1=Big endian) */
#define	CR1_S	0x0100	/* System protection */
#define	CR1_R	0x0200	/* ROM protection */
#define	CR1_I	0x1000	/* Instruction cache enable*/
#define	CR1_V	0x2000	/* High vector */
#define	CR1_RR	0x4000	/* Round robin cache */

/*
 * Fault status (CP15:CR5)
 */
#define	FSR_Alignment	0x1	/* 00x1 : Miss-alignment access */
#define	FSR_BusErrorT	0xc	/* 11x0 : Bus error when converting address */
#define	FSR_Translation	0x5	/* 01x1 : No page when converting address */
#define	FSR_Domain	0x9	/* 10x1 : Domain access violation */
#define	FSR_Permission	0xd	/* 11x1 : Access violation */
#define	FSR_BusErrorL	0x4	/* 01x0 : Bus error when fetching line */
#define	FSR_BusErrorO	0x8	/* 10x0 : Other bus errors */
#define	FSR_Section	0x0	/* xx0x : Section */
#define	FSR_Page	0x2	/* xx1x : Page */
#define	FSR_TypeMask	0xd	/* Type mask */

/* ------------------------------------------------------------------------ */

/*
 * Interrupt controller
 *	Register size W
 */
#define	ICU(n)		( 0xf8000200 + (n) )
					/* IRQ : Interrupt */
#define	IRQ_STS		ICU(0x000)	/* Valid interrupt status */
#define	IRQ_RSTS	ICU(0x004)	/* Occur interrupt status */
#define	IRQ_ENA		ICU(0x008)	/* Interrupt enable */
#define	IRQ_DIS		ICU(0x00c)	/* Interrupt disable */
#define	IRQ_SWI		ICU(0x010)	/* Software IRQ interrupt occur */
#define	IRQ_LEVEL	ICU(0x080)	/* Trigger mode (edge/level) */
#define IRQ_POLAR	ICU(0x084)	/* Trigger mode (polarity) */
#define	IRQ_CLR		ICU(0x088)	/* Interrupt clear (trigger reset) */
					/* FIQ : Fast Interrupt */
#define	FIQ_STS		ICU(0x100)	/* Valid interrupt status */
#define	FIQ_RSTS	ICU(0x104)	/* Occur interrupt status */
#define	FIQ_ENA		ICU(0x108)	/* Interrupt enable */
#define	FIQ_DIS		ICU(0x10c)	/* Interrupt disable */
#define	FIQ_LEVEL	ICU(0x180)	/* Trigger mode (edge/level) */
#define	FIQ_POLAR	ICU(0x184)	/* Trigger mode (polarity) */
#define	FIQ_CLR		ICU(0x188)	/* Interrupt clear (trigger reset) */

#define	IRQ_MSK(irq)	( 1 << (irq) )	/* IRQ 0-31 */
#define	FIQ_MSK(fiq)	( 1 << (fiq) )	/* FIQ 0-1  */

/*
 * GPIO register
 *	Register size W
 */
#define	GPIO(n)		( 0xf8000480 + (n) )
#define	GPIO_IRC	GPIO(0x030)	/* Interrupt setting */
					/* Port A interrupt relation */
#define	GPA_POLAR	GPIO(0x008)	/* Trigger mode (polarity) */
#define	GPA_LEVEL	GPIO(0x00c)	/* Trigger mode (edge/level) */
#define	GPA_ENA		GPIO(0x010)	/* Interrupt enable */
#define	GPA_STS		GPIO(0x014)	/* Interrupt status */
					/* Port B interrupt relation */
#define	GPB_POLAR	GPIO(0x020)	/* Trigger mode (polarity) */
#define	GPB_LEVEL	GPIO(0x024)	/* Trigger mode (edge/level) */
#define	GPB_ENA		GPIO(0x028)	/* Interrupt enable */
#define	GPB_STS		GPIO(0x02c)	/* Interrupt status */

/*
 * System register (FPGA interrupt)
 *	Register size B
 */
#define	IRQ_MASK1	0x07804028	/* Interrupt mask register 1*/
#define	IRQ_MASK2	0x0780402a	/* Interrupt mask register 2*/
#define	IRQ_STR1	0x0780402c	/* Interrupt status register 1*/
#define	IRQ_STR2	0x0780402e	/* Interrupt status register 2*/

/* ------------------------------------------------------------------------ */

/*
 * Software interrupt number for T-Kernel 
 */
#define	SWI_SVC		6	/* T-Kernel system call/extension SVC */
#define	SWI_RETINT	7	/* tk_ret_int() system call */
#define	SWI_DISPATCH	8	/* Task dispatcher */
#define	SWI_DEBUG	9	/* Debugger support function */

/*
 * Software interrupt number for T-Monitor
 */
#define	SWI_MONITOR	4	/* T-Monitor service call */

/*
 * Software interrupt number for Extension
 */
#define	SWI_KILLPROC	11	/* Force process termination request */

/* ------------------------------------------------------------------------ */

/*
 * Location and size of task specific space
 *	Number of entries and index number of first level page table
 */
#define	TOP_PDIR_ENTRIES	1024	/* 0x40000000 */
#define	NUM_PDIR_ENTRIES	256	/* 0x40000000 - 0x50000000 */

#endif /* __TK_SYSDEF_DEPEND_H__ */