syslib_depend.h

日本著名的的嵌入式实时操作系统T-Kernel的源码及用户手册。

/*
 *----------------------------------------------------------------------
 *    T-Kernel
 *
 *    Copyright (C) 2004 by Ken Sakamura. All rights reserved.
 *    T-Kernel is distributed under the T-License.
 *----------------------------------------------------------------------
 *
 *    Version:   1.01.00
 *    Released by T-Engine Forum(http://www.t-engine.org) at 2004/6/28.
 *
 *----------------------------------------------------------------------
 */

/*
 *	@(#)syslib_depend.h (tk/VR4131)
 *
 *	T-Kernel/SM VR4131 Library
 */

#ifndef __TK_SYSLIB_DEPEND_H__
#define __TK_SYSLIB_DEPEND_H__

#include <tk/errno.h>

#ifdef __cplusplus
extern "C" {
#endif

/*
 * CPU interrupt control
 *	'intsts' is the value of the status register (PSR) in CP0
 *	disint()  Set PSR.IE = 0 and return the original ~PSR to the
 *	return value.
 *	enaint()  Set PSR.IE = ~intsts.IE. Do not change except for PSR.IE.
 *		  Return the original ~PSR to the return value.
 */
IMPORT UINT disint( void );
IMPORT UINT enaint( UINT intsts );
#define	DI(intsts)	( (intsts) = disint() )
#define	EI(intsts)	( enaint(intsts) )
#define	isDI(intsts)	( ((intsts) & 0x0001) != 0 )

/*
 * Interrupt vector
 *	The interrupt vector is the index number of the vector table.
 */
typedef UINT	INTVEC;

/* Convert to interrupt definition number */
#define	DINTNO(intvec)	(intvec)

/* ------------------------------------------------------------------------ */
/*
 *	VR4131 Interrupt controller-related
 */

/*
 * Interrupt vector (INTVEC) value
 *	The values that can be specified as 'intvec' among interrupt
 *	controller operation functions are in the range of IRQ, GPIO
 *	and FPGA interrupts. 
 *	However, some functions can not be specified.
 *	If any others out of the available range are specified,
 *	the operation can not be guaranteed.
 *
 *	Also, the operation in the interrupt controller 's level 2
 *	register can not be supported.
 *	For the level 2 register, need to operate the register directly.
 *
 *	The operation for GPIO interrupt is done for GPIO controller (GIU).
 */
#define	IV_IRQ(n)	(  95 - (n) )	/* Interrupt controller  0-31 */
#define	IV_GPIO(n)	( 127 - (n) )	/* GPIO Interrupt  0-31 */
#define	IV_FPGA(n)	( 159 - (n) )	/* FPGA Interrupt  0-31 */

/*
 * Interrupt mode setting
 *	Set the interrupt specified by 'intvec' to the mode specified
 *	by 'mode.'
 *
 *	mode := (IM_LEVEL || IM_EDGE) | (IM_HI || IM_LOW)
 *
 *	Settable 'intvec' is only GPIO interrupt.
 *
 *	Hold/through select register is set as follows:
 *	Edge trigger	Hold
 *	Level trigger	Through
 */
IMPORT void SetIntMode( INTVEC intvec, UINT mode );

#define	IM_LEVEL	0	/* level trigger */
#define	IM_EDGE		1	/* edge  trigger */
#define	IM_HI		2	/* high level trigger/positive edge trigger */
#define	IM_LOW		0	/* low  level trigger/negagive edge trigger */

/*
 * Interrupt enable
 *	Enable the interrupt specified by 'intvec.'
 *
 *	IRQ and GPIO interrupts can be specified by 'intvec.'
 *	FPGA interrupt can not be specified. Need to operate FPGA
 *	register directly.
 */
IMPORT void EnableInt( INTVEC intvec );

/*
 * Interrupt disable
 *	Disable the interrupt specified by 'intvec.'
 *
 *	IRQ and GPIO interrupts can be specified by 'intvec.'
 *	FPGA interrupt can not be specified. Need to operate FPGA
 *	register directly.
 */
IMPORT void DisableInt( INTVEC intvec );

/*
 * Clear interrupt request
 *	Clear the interrupt request specified by 'intvec.'
 *	Only GPIO interrupt can be specified as 'intvec.'
 *
 *	Available only for edge trigger.
 *	For edge trigger, need to clear the interrupt with interrupt
 *	handler.
 */
IMPORT void ClearInt( INTVEC intvec );

/*
 * Check for existence of interrupt request
 *	Check whether there is an interrupt request specified by 'intvec.'
 *	If there is an interrupt request, return TRUE (except 0).
 */
IMPORT BOOL CheckInt( INTVEC intvec );

/*
 * Issue EOI(End Of Interrupt)
 */
#define	EndOfInt(intvec)

/* ------------------------------------------------------------------------ */

/*
 * I/O port access
 *	Only memory mapped I/O for VR
 */
Inline void out_w( INT port, UW data )
{
	Asm("sw %0, (%1)":: "r"(data), "r"(port));
}
Inline void out_h( INT port, UH data )
{
	Asm("sh %0, (%1)":: "r"(data), "r"(port));
}
Inline void out_b( INT port, UB data )
{
	Asm("sb %0, (%1)":: "r"(data), "r"(port));
}

Inline UW in_w( INT port )
{
	UW	data;
	Asm("lw %0, (%1)": "=r"(data): "r"(port));
	return data;
}
Inline UH in_h( INT port )
{
	UH	data;
	Asm("lhu %0, (%1)": "=r"(data): "r"(port));
	return data;
}
Inline UB in_b( INT port )
{
	UB	data;
	Asm("lbu %0, (%1)": "=r"(data): "r"(port));
	return data;
}

#ifdef __cplusplus
}
#endif
#endif /* __TK_SYSLIB_DEPEND_H__ */