sysdef_depend.h

日本著名的的嵌入式实时操作系统T-Kernel的源码及用户手册。

/*
 *----------------------------------------------------------------------
 *    T-Kernel
 *
 *    Copyright (C) 2004 by Ken Sakamura. All rights reserved.
 *    T-Kernel is distributed under the T-License.
 *----------------------------------------------------------------------
 *
 *    Version:   1.01.00
 *    Released by T-Engine Forum(http://www.t-engine.org) at 2004/6/28.
 *
 *----------------------------------------------------------------------
 */

/*
 *	@(#)sysdef_depend.h (tk/VR4131)
 *
 *	Definition about VR4131
 *
 *	Included from assembler source.
 */

#ifndef __TK_SYSDEF_DEPEND_H__
#define __TK_SYSDEF_DEPEND_H__

/*
 * System control coprocessor (CP0)
 */
#define	CP0_IDX		0	/* TLB: Index */
#define	CP0_RND		1	/* TLB: Random */
#define	CP0_ELO0	2	/* TLB: Entry Lo0 */
#define	CP0_ELO1	3	/* TLB: Entry Lo1 */
#define	CP0_CTX		4	/* EXC: Context */
#define	CP0_PMSK	5	/* TLB: Pagemask */
#define	CP0_WIR		6	/* TLB: Wired */
#define	CP0_BVA		8	/* EXC: BadVAddr */
#define	CP0_CNT		9	/* EXC: Count */
#define	CP0_EHI		10	/* TLB: Entry Hi */
#define	CP0_CMP		11	/* EXC: Comparison */
#define	CP0_PSR		12	/* EXC: Status */
#define	CP0_OCC		13	/* EXC: Cause */
#define	CP0_EPC		14	/* EXC: EPC */
#define	CP0_PRID	15	/* MMU: PRId */
#define	CP0_CFG		16	/* MMU: Config */
#define	CP0_LLA		17	/* MMU: LLAddr */
#define	CP0_WLO		18	/* EXC: Watch Lo */
#define	CP0_WHI		19	/* EXC: Watch Hi */
#define	CP0_XCTX	20	/* EXC: X Context */
#define	CP0_PURF	25	/* EXC: Performance counter */
#define	CP0_ECC		26	/* EXC: Parity error */
#define	CP0_CACH	27	/* EXC: Cache error */
#define	CP0_TLO		28	/* MMU: Tag Lo */
#define	CP0_THI		29	/* MMU: Tag Hi */
#define	CP0_EEPC	30	/* EXC: Error EPC */

/*
 * Status register (CP0_PSR)
 */
#define	SR_XX	0x80000000	/* MIPS4 instruction use enable on user mode */
#define	SR_CU2	0x40000000	/* Coprocessor 2 use enable */
#define	SR_CU1	0x20000000	/* Coprocessor 1 (FPU) use enable */
#define	SR_CU0	0x10000000	/* Coprocessor 0 (CP0) use enable */
#define	SR_FR	0x04000000	/* Number of available floating point registers (1=32) */
#define	SR_RE	0x02000000	/* Endian conversion on user mode (always 0) */

#define	SR_DS	0x01ff0000	/* Self-diagnosis status area */
#define	SR_DME	0x01000000	/* Transfer enable to debug mode */
#define	SR_BEV	0x00400000	/* Exception vector base address setting */
#define	SR_TS	0x00200000	/* TLB shutdown occur */
#define	SR_SR	0x00100000	/* Soft reset or NMI occur */
#define	SR_CH	0x00040000	/* CP0 condition bit */
#define	SR_CE	0x00020000	/* Cache setting */
#define	SR_DE	0x00010000	/* Cache error exception enable */

#define	SR_IMMSK 0x0000ff00	/* Interrupt mask */
#define	SR_IM(n) (0x100 << (n))	/* (n = 0-7) */
#define	SR_KX	0x00000080	/* 64 bits enable on Kernel mode */
#define	SR_SX	0x00000040	/* 64 bits enable on supervisor mode */
#define	SR_UX	0x00000020	/* 64 bits enable on user mode */
#define	SR_KSU	0x00000018	/* Operating mode */
#define	SR_KNL	0x00000000	/* KSU: Kernel mode */
#define	SR_SVC	0x00000008	/* KSU: Supervisor mode */
#define	SR_USR	0x00000010	/* KSU: User mode */
#define	SR_ERL	0x00000004	/* Error level */
#define	SR_EXL	0x00000002	/* Exception level */
#define	SR_IE	0x00000001	/* Interrupt enable */

/*
 * Cause register (CP0_OCC)
 */
#define	OC_BD	0x80000000	/* Exception in delayed slot */
#define	OC_CE	0x30000000	/* Disabled exception coprocessor number */
#define	OC_IPMSK 0x0000ff00	/* Occurring interrupt */
#define	OC_IP(n) (0x100 << (n))	/* (n = 0-7) */
#define	OC_EXC	0x0000007c	/* Exception code */

/*
 * Task mode flag
 *	System shared information taskmode
 */
#define	TMF_CPL(n)	(n)		/* CPL: Current protection level 0-3 */
#define	TMF_PPL(n)	( (n) << 16 )	/* PPL: Previous protection level 0-3 */

/* ------------------------------------------------------------------------ */
/*
 *	VR4131 interrupt-related
 */

/*
 * Base address
 */
#define	INTCS_BASE	0xaf000000	/* Int. register base address */
#define	IOCS0_BASE	0xaa000000	/* Ext. I/O area 0 (CS0) */

/*
 * Interrupt controller
 *	Register size H
 */
#define	ICU(n)		( INTCS_BASE + (n) )

#define	SYSINT1REG	ICU(0x0080)	/* System interrupt status 1 */
#define	SYSINT2REG	ICU(0x00a0)	/* System interrupt status 2 */
#define	MSYSINT1REG	ICU(0x008c)	/* System interrupt mask 1 */
#define	MSYSINT2REG	ICU(0x00a6)	/* System interrupt mask 2 */

#define	GIUINTLREG	ICU(0x0088)	/* GPIO interrupt status L */
#define	GIUINTHREG	ICU(0x00a2)	/* GPIO interrupt status H */
#define	MGIUINTLREG	ICU(0x0094)	/* GPIO interrupt mask L */
#define	MGIUINTHREG	ICU(0x00a8)	/* GPIO interrupt mask H */

/*
 * GPIO register (interrupt)
 *	Register size H
 */
#define	GIU(n)		( INTCS_BASE + (n) )

#define	GIUINTSTATL	GIU(0x0148)	/* Interrupt status L */
#define	GIUINTSTATH	GIU(0x014a)	/* Interrupt status H */
#define	GIUINTENL	GIU(0x014c)	/* Interrupt enable L*/
#define	GIUINTENH	GIU(0x014e)	/* Interrupt enable H */
#define	GIUINTTYPL	GIU(0x0150)	/* Interrupt type L */
#define	GIUINTTYPH	GIU(0x0152)	/* Interrupt type H */
#define	GIUINTALSELL	GIU(0x0154)	/* Active level select L */
#define	GIUINTALSELH	GIU(0x0156)	/* Active level select H */
#define	GIUINTHTSELL	GIU(0x0158)	/* Hold/through select L */
#define	GIUINTHTSELH	GIU(0x015a)	/* Hold/through select H */

/*
 * FPGA interrupt controller
 */
#define	FPGA(n)		( IOCS0_BASE + (n) )

#define	INT_PEND	FPGA(0x0a20)	/* Interrupt status */

/* ------------------------------------------------------------------------ */

/*
 * SYSCALL number for T-Monitor
 */
#define	CALL_MONITOR	37	/* T-Monitor service call */
#define	CALL_MONBREAK	42	/* T-Monitor break point */

/*
 * SYSCALL number for T-Kernel
 */
#define	CALL_SVC	38	/* T-Kernel system call/extension SVC */
#define	CALL_RETTEX	39	/* Return from task exception handler */
#define	CALL_DEBUG	40	/* Debugger support function */

/*
 * SYSCALL number for Extension
 */
#define	CALL_KILLPROC	41	/* Force process termination request */

#endif /* __TK_SYSDEF_DEPEND_H__ */