asm_depend.h

日本著名的的嵌入式实时操作系统T-Kernel的源码及用户手册。

/*
 *----------------------------------------------------------------------
 *    T-Kernel
 *
 *    Copyright (C) 2004 by Ken Sakamura. All rights reserved.
 *    T-Kernel is distributed under the T-License.
 *----------------------------------------------------------------------
 *
 *    Version:   1.01.00
 *    Released by T-Engine Forum(http://www.t-engine.org) at 2004/6/28.
 *
 *----------------------------------------------------------------------
 */

/*
 *	@(#)asm_depend.h (tk/VR4131)
 *
 *	Assembler Macro for VR4131
 */

#ifndef __TK_ASM_DEPEND_H__
#define __TK_ASM_DEPEND_H__

#define	slow(n)		( ((n) << 48) / 0x1000000000000 )
#define	shigh(n)	( ((n) - slow(n)) / 0x10000 )

/*
 * Register name
 *	('at,' 'kt0,' 'kt1,' 'gp,' 'sp,' and 'fp' are supported by assembler)
 */
#define	zero	0
#define	v0	2
#define	v1	3
#define	a0	4
#define	a1	5
#define	a2	6
#define	a3	7
#define	t0	8
#define	t1	9
#define	t2	10
#define	t3	11
#define	t4	12
#define	t5	13
#define	t6	14
#define	t7	15
#define	s0	16
#define	s1	17
#define	s2	18
#define	s3	19
#define	s4	20
#define	s5	21
#define	s6	22
#define	s7	23
#define	t8	24
#define	t9	25
#define	ra	31

/* ------------------------------------------------------------------------ */
/*
 *	'nop' instruction for pipeline hazard preparation
 *
 *	(Example)
 *	mtc0	$t0, $CP0_PSR	// Interrupt disable
 *	NOP(HzD_MTC0 - HzS_INT)	// Interrupt disable determine wait
 */

 .macro _nop n
	.if \n > 0
	nop
	_nop	\n - 1
	.endif
 .endm

#define	NOP(n)		_nop	((n) - 1)
				/* D:Destination S:Source */
#define	HzD_MTC0	6	/* D: mtc0 instruction */
#define	HzS_MFC0	4	/* S: mfc0 instruction */
#define	HzS_TLBR	3	/* S: tlbr instruction */
#define	HzD_TLBR	6	/* D: tlbr instruction */
#define	HzS_TLBW	3	/* S: tlbwi, tlbwr instruction */
#define	HzD_TLBW	6	/* D: tlbwi, tlbwr instruction */
#define	HzS_TLBP	3	/* S: tlbp instruction */
#define	HzD_TLBP	6	/* D: tlbp instruction */
#define	HzS_ERET	5	/* S: eret instruction */
#define	HzD_CACHE_L	6	/* D: cache index load tag */
#define	HzS_CACHE_S	4	/* S: cache index store tag */
#define	HzS_CACHE_H	4	/* S: cache hit operation */
#define	HzD_CACHE_H	6	/* D: cache hit operation */
#define	HzS_CU		2	/* S: coprocessor use */
#define	HzS_FETCH	2	/* S: instruction fetch */
#define	HzS_INT		2	/* S: interrupt */
#define	HzS_MEM		4	/* S: load/store */

/* ------------------------------------------------------------------------ */
/*
 *	System shared information
 */

#define	SCINFO		0x80000280	/* System shared information */
#define	ISTKPOS		(SCINFO + 4*4)	/* Exception stack pointer */
#define	SSTKTOP		(SCINFO + 5*4)	/* System stack top */
#define	TASKMODE	(SCINFO + 6*4)	/* Task mode flag */

/* ------------------------------------------------------------------------ */
/*
 *	Exception restore
 */

/*
 * Exception/Interrupt Return
 *	Exception Stack State
 *		+---------------+
 *	isp  ->	| t8:$24	|
 *	   +8	| t9:$25	|
 *	   +16	| EPC		|
 *	   +24	| PSR||taskmode	| Upper:PSR  Lower:taskmode
 *		+---------------+
 *	   +32	| usp		|
 *		+---------------+
 */
 .macro EIT_RETURN name
	.set	push
	.set	noat
	.set	noreorder

	// For VR4131, the mode can not be switched properly unless
	// you change KSU after setting EXL=1 and waiting for more than
	// 5 instructions. Therefore set EXL=1 first before restoring
	// the entire PSR and wait until the processor mode is determined.
	mfc0	$t8, $CP0_PSR
	li	$t9, ~SR_IE
	and	$t8, $t8, $t9
	mtc0	$t8, $CP0_PSR		// IE=0 Interrupt disable
	NOP(HzD_MTC0 - HzS_INT - 1)	// Interrupt disable is determined
	or	$t8, $t8, SR_EXL	// EXL=1
	mtc0	$t8, $CP0_PSR		// Do not change KSU during waiting
					// for at least 5 instructions

	lui	$t8, shigh(SCINFO)
	lw	$t9, slow(ISTKPOS)($t8)
	ld	$t9, 3*8($t9)		// PSR||taskmode
	sw	$t9, slow(TASKMODE)($t8)// taskmode restore 
	dsra	$kt0, $t9, 32
	mtc0	$kt0, $CP0_PSR		// PSR restore
					// (EXL = 1 Interrupt disable)

	lw	$kt1, slow(ISTKPOS)($t8)// kt1 = isp
	and	$kt0, $t9, TMF_CPL(3)
	beqz	$kt0, e_nostkchg_\name
	li	$kt0, 4*8		// Stack usage (without stack switch)

	ld	$sp, 4*8($kt1)		// sp restore (Return to user stack)
	li	$kt0, 5*8		// Stack usage (with stack switch)

  e_nostkchg_\name:
	ld	$t9, 2*8($kt1)
	dmtc0	$t9, $CP0_EPC		// EPC restore
	ld	$t9, 1*8($kt1)		// t9 restore
	ld	$t8, 0*8($kt1)		// t8 restore

	addu	$kt1, $kt1, $kt0	// isp update
	lui	$kt0, shigh(ISTKPOS)
	sw	$kt1, slow(ISTKPOS)($kt0)
	eret
	.set	pop
 .endm

/*
 * Return from SYSCALL
 *	Exception Stack State
 *		+---------------+
 *	isp  ->	| t8:$24	|
 *	   +8	| t9:$25	|
 *	   +16	| EPC		|
 *	   +24	| PSR||taskmode	| Upper:PSR  Lower:taskmode
 *		+---------------+
 *	   +32	| usp		|
 *		+---------------+
 *
 *	Difference from EIT_RETURN
 *	PSR restore from a stack is only the lower 16 bits.
 *	Leave the upper 16-bit unchanged.
 */
 .macro CALL_RETURN name
	.set	push
	.set	noat
	.set	noreorder

	// For VR4131, the mode can not be switched properly unless you
	// change KSU after setting EXL=1 and waiting for more than
	// 5 instructions. Therefore set EXL=1 first before restoring
	// the entire PSR and wait until the processor mode is determined.
	mfc0	$t8, $CP0_PSR
	li	$t9, ~SR_IE
	and	$t8, $t8, $t9
	mtc0	$t8, $CP0_PSR		// IE=0 Interrupt disable
	NOP(HzD_MTC0 - HzS_INT - 1)	// Interrupt disable is determined
	or	$t8, $t8, SR_EXL	// EXL=1
	mtc0	$t8, $CP0_PSR		// Do not change KSU during waiting
					// for at least 5 instructions

	lui	$t8, shigh(SCINFO)
	lw	$t9, slow(ISTKPOS)($t8)
	ld	$t9, 3*8($t9)		// PSR||taskmode
	sw	$t9, slow(TASKMODE)($t8)// taskmode restore 
	mfc0	$kt1, $CP0_PSR		// Only lower 16 bits of PSR
	dsll	$kt0, $t9, 16		// Restore from stack
	dsrl	$kt0, $kt0, 16+32
	srl	$kt1, $kt1, 16
	sll	$kt1, $kt1, 16
	or	$kt0, $kt0, $kt1
	mtc0	$kt0, $CP0_PSR		// PSR restore
					// (EXL = 1 interrupt disable)

	lw	$kt1, slow(ISTKPOS)($t8)// kt1 = isp
	and	$kt0, $t9, TMF_CPL(3)
	beqz	$kt0, c_nostkchg_\name
	li	$kt0, 4*8		// Stack usage (without stack switch)

	ld	$sp, 4*8($kt1)		// sp restore (Return to user stack)
	li	$kt0, 5*8		// Stack usage (with stack switch)

  c_nostkchg_\name:
	ld	$t9, 2*8($kt1)
	dmtc0	$t9, $CP0_EPC		// EPC restore
	ld	$t9, 1*8($kt1)		// t9 restore
	ld	$t8, 0*8($kt1)		// t8 restore

	addu	$kt1, $kt1, $kt0	// isp update
	lui	$kt0, shigh(ISTKPOS)
	sw	$kt1, slow(ISTKPOS)($kt0)
	eret
	.set	pop
 .endm

/* ------------------------------------------------------------------------ */
/*
 *	Movement between Exception Stack and System Stack
 *
 *	Stack Contents
 *		+---------------+
 *	sp  ->	| t8:$24	|
 *	   +8	| t9:$25	|
 *	   +16	| EPC		|
 *	   +24	| PSR||taskmode	| Upper:PSR  Lower:taskmode
 *		+---------------+
 *	   +32	| usp		|
 *		+---------------+
 */

/*
 * ISP -> SSP move
 */
 .macro MOVE_ISP_SSP name
	.set	push
	.set	noat
	.set	reorder
	lw	$t8, ISTKPOS
	ld	$t9, 3*8($t8)	// PSR||taskmode
	and	$t9, $t9, TMF_CPL(3)
	subu	$sp, $sp, 4*8
	beqz	$t9, nousp1_\name

	subu	$sp, $sp, 1*8
	ld	$t9, 4*8($t8)	// usp move
	sd	$t9, 4*8($sp)

  nousp1_\name:
	ld	$t9, 0*8($t8)	// t8 move
	sd	$t9, 0*8($sp)
	ld	$t9, 1*8($t8)	// t9 move
	sd	$t9, 1*8($sp)
	ld	$t9, 2*8($t8)	// EPC move
	sd	$t9, 2*8($sp)
	ld	$t9, 3*8($t8)	// PSR||taskmode move
	sd	$t9, 3*8($sp)

	and	$t9, $t9, TMF_CPL(3)
	addu	$t8, $t8, 4*8
	beqz	$t9, nousp2_\name
	addu	$t8, $t8, 1*8

  nousp2_\name:
	lui	$t9, shigh(ISTKPOS)
	sw	$t8, slow(ISTKPOS)($t9)
	.set	pop
 .endm

/*
 * SSP -> ISP move
 */
 .macro MOVE_SSP_ISP name
	.set	push
	.set	noat
	.set	reorder
	lw	$t8, ISTKPOS
	ld	$t9, 3*8($sp)	// PSR||taskmode
	and	$t9, $t9, TMF_CPL(3)
	subu	$t8, $t8, 4*8
	.set	noreorder
	beqz	$t9, nousp3_\name
	lui	$t9, shigh(ISTKPOS)
	.set	reorder

	subu	$t8, $t8, 1*8
	sw	$t8, slow(ISTKPOS)($t9)

	ld	$t9, 4*8($sp)	// usp move
	sd	$t9, 4*8($t8)
	j	l1_\name

  nousp3_\name:
	sw	$t8, slow(ISTKPOS)($t9)

  l1_\name:
	ld	$t9, 0*8($sp)	// t8 move
	sd	$t9, 0*8($t8)
	ld	$t9, 1*8($sp)	// t9 move
	sd	$t9, 1*8($t8)
	ld	$t9, 2*8($sp)	// EPC move
	sd	$t9, 2*8($t8)
	ld	$t9, 3*8($sp)	// PSR||taskmode move
	sd	$t9, 3*8($t8)

	and	$t9, $t9, TMF_CPL(3)
	addu	$sp, $sp, 4*8
	beqz	$t9, nousp4_\name
	addu	$sp, $sp, 1*8

  nousp4_\name:
	.set	pop
 .endm

/* ------------------------------------------------------------------------ */
/*
 *	Task exception handler entry
 *
 *		+---------------+
 *	usp ->	|texcd		| Exception code
 *	   +8	|PC		| Return address from handler
 *		+---------------+
 */
 .macro TEXHDR_ENTRY texhdr
	.set	push
	.set	noat
	.set	reorder
	subu	$sp, $sp, 24*8
	sd	$at,   4*8($sp)		// Register save
	sd	$v0,   5*8($sp)
	sd	$v1,   6*8($sp)
	sd	$a0,   7*8($sp)
	sd	$a1,   8*8($sp)
	sd	$a2,   9*8($sp)
	sd	$a3,  10*8($sp)
	sd	$t0,  11*8($sp)
	sd	$t1,  12*8($sp)
	sd	$t2,  13*8($sp)
	sd	$t3,  14*8($sp)
	sd	$t4,  15*8($sp)
	sd	$t5,  16*8($sp)
	sd	$t6,  17*8($sp)
	sd	$t7,  18*8($sp)
	sd	$t8,  19*8($sp)
	sd	$t9,  20*8($sp)
	sd	$gp,  21*8($sp)
	sd	$ra,  22*8($sp)
	ld	$a0,  24*8($sp)		// texcd
	mflo	$t0
	mfhi	$t1
	sd	$t0,  23*8($sp)
	sd	$t1,  24*8($sp)

	jal	\texhdr			// call texhdr(texcd)

	ld	$t0,  23*8($sp)		// Register restore
	ld	$t1,  24*8($sp)
	mtlo	$t0
	mthi	$t1
	ld	$at,   4*8($sp)
	ld	$v0,   5*8($sp)
	ld	$v1,   6*8($sp)
	ld	$a0,   7*8($sp)
	ld	$a1,   8*8($sp)
	ld	$a2,   9*8($sp)
	ld	$a3,  10*8($sp)
	ld	$t0,  11*8($sp)
	ld	$t1,  12*8($sp)
	ld	$t2,  13*8($sp)
	ld	$t3,  14*8($sp)
	ld	$t4,  15*8($sp)
	ld	$t5,  16*8($sp)
	ld	$t6,  17*8($sp)
	ld	$t7,  18*8($sp)
	ld	$t8,  19*8($sp)
	ld	$t9,  20*8($sp)
	ld	$gp,  21*8($sp)
	ld	$ra,  22*8($sp)
	addu	$sp, $sp, 25*8

	syscall	CALL_RETTEX
	.set	pop
 .endm

/* ------------------------------------------------------------------------ */
#endif /* __TK_ASM_DEPEND_H__ */