syslib_depend.h

日本著名的的嵌入式实时操作系统T-Kernel的源码及用户手册。

/*
 *----------------------------------------------------------------------
 *    T-Kernel
 *
 *    Copyright (C) 2004 by Ken Sakamura. All rights reserved.
 *    T-Kernel is distributed under the T-License.
 *----------------------------------------------------------------------
 *
 *    Version:   1.01.00
 *    Released by T-Engine Forum(http://www.t-engine.org) at 2004/6/28.
 *
 *----------------------------------------------------------------------
 */

/*
 *	@(#)syslib_depend.h (tk/M32104)
 *
 *	T-Kernel/SM M32104 Library
 */

#ifndef __TK_SYSLIB_DEPEND_H__
#define __TK_SYSLIB_DEPEND_H__

#include <tk/errno.h>

#ifdef __cplusplus
extern "C" {
#endif

/*
 * CPU interrupt control
 *	'intsts' is the value to which the value in CPU's PSW register
 *	is reversed (NOT)
 *	disint()  Set PSW.IE = 0 and return the original ~PSW to the
 *		  return value.
 *	enaint()  Set PSW.IE = ~intsts.IE. Do not change except for PSW.IE.
 *		  Return the original ~PSW to the return value.
 */
IMPORT UINT disint( void );
IMPORT UINT enaint( UINT intsts );
#define	DI(intsts)	( (intsts) = disint() )
#define	EI(intsts)	( enaint(intsts) )
#define	isDI(intsts)	( ((intsts) & 0x0040) != 0 )

/*
 * Interrupt vector
 *	The interrupt vector is the index number of the vector table.
 */
typedef UINT	INTVEC;

/* Convert to interrupt definition number */
#define	DINTNO(intvec)	(intvec)

/*
 * Interrupt vector value (part)
 */
typedef enum intvec {
	IV_SBI		= 1,		/* System break */
	IV_INT0		= 20 + 1,	/* Interrupt request from ext. bus */
	IV_INT1		= 20 + 2,	/* Interrupt request from PLD */
	IV_INT2		= 20 + 3,
	IV_INT3		= 20 + 4,
	IV_INT4		= 20 + 5,
	IV_INT5		= 20 + 6,	/* Power switch */
	IV_INT6		= 20 + 7,
	IV_INT7		= 20 + 8,
	IV_INT8		= 20 + 9,
	IV_INT9		= 20 + 10,
	IV_INT10	= 20 + 11,
	IV_INT11	= 20 + 12,
	IV_INT12	= 20 + 13,
	IV_INT13	= 20 + 14,
	IV_INT14	= 20 + 15,
	IV_MFT0		= 20 + 16,
	IV_MFT1		= 20 + 17,
	IV_MFT2		= 20 + 18,
	IV_MFT3		= 20 + 19,
	IV_MFTX0	= 20 + 24,
	IV_MFTX1	= 20 + 25,
	IV_DMA0		= 20 + 32,
	IV_DMA1		= 20 + 33,
	IV_DMA2		= 20 + 34,
	IV_DMA3		= 20 + 35,
	IV_SIO0R	= 20 + 40,
	IV_SIO0S	= 20 + 41,
	IV_SIO1R	= 20 + 42,
	IV_SIO1S	= 20 + 43,
	IV_SIO2R	= 20 + 44,
	IV_SIO2S	= 20 + 45,
	IV_SIO3R	= 20 + 46,
	IV_SIO3S	= 20 + 47,
	IV_SIO4R	= 20 + 48,
	IV_SIO4S	= 20 + 49,
	IV_ADC		= 20 + 56,
	IV_I2C		= 20 + 57,
	IV_WKUP		= 20 + 63,
	IV_CFIREQ	= 84 + 3,	/* CFIREQ# (CF ext. terminal) */
	IV_CFCINS	= 84 + 4,	/* CFC card insert */
	IV_CFCEJECT	= 84 + 5,	/* CFC card remove */
	IV_EXINT	= 84 + 6,	/* Ext. interrupt (EXINT# terminal) */
	IV_MMC		= 84 + 11,	/* MMC card insert/eject */
	IV_SCER		= 84 + 13,	/* SC error */
	IV_SCR		= 84 + 14,	/* SC receiver */
	IV_SCS		= 84 + 15	/* SC send */
} IntVec;

/*
 * Interrupt controller control
 *	Only the range of 20(IV_INT0)-115 can be specified by 'intvec.'
 *	If any others out of the available range are specified,
 *	the operation can not be guaranteed.
 */
/*
 * Interrupt mode setting
 *	Set the interrupt specified by 'intvec' to the mode specified
 *	by 'mode.' 
 *	Depending the interrupt type (intvec), some modes can not be set.
 *	Set the mode value to the interrupt control register
 */
IMPORT void SetIntMode( INTVEC intvec, UINT mode );

#define	ISMOD_EDGE_D	0x00	/* Fall edge sense */
#define	ISMOD_LEVEL_L	0x10	/* Low level sense */
#define	ISMOD_EDGE_U	0x20	/* Raise edge sense */
#define	ISMOD_LEVEL_H	0x30	/* High level sense */
#define	ISMOD_EDGE_UD	0x40	/* Rise/Fall edges sense */

/*
 * Interrupt enable
 *	Enable the interrupt specified by 'intvec' according to the
 *	'level' priority.
 *	'level' is between 0-7. (For 7, the interrupt is practically
 *	disabled)
 *	Set the following bits of the interrupt control register:
 *	IEN = 1 (interrupt request accept enable)
 *	ILEVEL = level
 *	Do not change other bits except for these.
 */
IMPORT void EnableInt( INTVEC intvec, INT level );

/*
 * Interrupt disable
 *	Disable the interrupt specified by 'intvec.'
 *	Set the following bits of the interrupt control register:
 *	ILEVEL = 7
 *	Do not change other bits except for this (IEN does not change).
 */
IMPORT void DisableInt( INTVEC intvec );

/*
 * Clear interrupt request
 *	Clear the interrupt request specified by 'intvec.'
 *	Set the following bits of the interrupt control register:
 *	IREQ = 1
 *	Do not change except for these bits.
 */
IMPORT void ClearInt( INTVEC intvec );

/*
 * Check for existence of interrupt request
 *	Read the interrupt request register and check whether there
 *	is an interrupt request specified by 'intvec.'
 *	If there is an interrupt request, return TRUE (0 except).
 */
IMPORT BOOL CheckInt( INTVEC intvec );

/*
 * Issue EOI(End Of Interrupt)
 */
#define	EndOfInt(intvec)

/* ------------------------------------------------------------------------ */

/*
 * I/O port access
 *	Only memory mapped I/O for M32R
 */
Inline void out_w( INT port, UW data )
{
	Asm("st %0, @%1":: "r"(data), "r"(port));
}
Inline void out_h( INT port, UH data )
{
	Asm("sth %0, @%1":: "r"(data), "r"(port));
}
Inline void out_b( INT port, UB data )
{
	Asm("stb %0, @%1":: "r"(data), "r"(port));
}

Inline UW in_w( INT port )
{
	UW	data;
	Asm("ld %0, @%1": "=r"(data): "r"(port));
	return data;
}
Inline UH in_h( INT port )
{
	UH	data;
	Asm("lduh %0, @%1": "=r"(data): "r"(port));
	return data;
}
Inline UB in_b( INT port )
{
	UB	data;
	Asm("ldub %0, @%1": "=r"(data): "r"(port));
	return data;
}

/*
 * I/O port access (for CF card)
 *	Normal I/O access is available, but I/O access such as
 *	'in_[bwh]()' should be used in this case.
 */
IMPORT void cf_out_h( INT port, UH data );
IMPORT void cf_out_b( INT port, UB data );
IMPORT UH   cf_in_h( INT port );
IMPORT UB   cf_in_b( INT port );

#ifdef __cplusplus
}
#endif
#endif /* __TK_SYSLIB_DEPEND_H__ */