📄 _disint.s
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/* *---------------------------------------------------------------------- * T-Kernel * * Copyright (C) 2004 by Ken Sakamura. All rights reserved. * T-Kernel is distributed under the T-License. *---------------------------------------------------------------------- * * Version: 1.01.00 * Released by T-Engine Forum(http://www.t-engine.org) at 2004/6/28. * *---------------------------------------------------------------------- *//* * @(#)_disint.S (libtk/VR5500) * * Enable/disable external interrupt for library internal use */#include <machine.h>#include <tk/asm.h>/* * Disable external interrupt * UINT _disint( void ) * PSR.IE = 0; return value is PSR prior to change. */ .text .balign 4 .globl Csym(_disint) .type Csym(_disint), @functionCsym(_disint): mfc0 $v0, $CP0_PSR and $t0, $v0, ~(SR_IE|SR_CU1) mtc0 $t0, $CP0_PSR NOP(HzD_MTC0 - HzS_INT - 1) jr $ra/* * Enable external interrupt (restore to original state) * void _enaint( UINT intsts ) * Set instst in PSR. */ .text .balign 4 .globl Csym(_enaint) .type Csym(_enaint), @functionCsym(_enaint): and $a0, $a0, ~SR_CU1 mtc0 $a0, $CP0_PSR NOP(HzD_MTC0 - HzS_INT - 1) jr $ra/* * (NB:) CU1 setting while FPU is present * CU1 is used for FPU context switching, and can potentially * change at any time * while task dispatch is enabled. Thus, CU1 may change to 0 * after PSR is read. If as a result CU1 = 1 is incorrectly * set during the write to PSR, this will cause the wrong FPU * context to be used. * Since PSR cannot be exclusively updated (read -> update -> write), * this problem can be avoided by ensuring that CU1 = 0 at * all times when writing to PSR. */
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