psc_drv.h

DSP, 三相交流异步电机控制程序, C语言, 空间矢量SPWM, 内含PI算法及三相桥开关控制

      //! @}

      //! @defgroup PSC2_clock_control PSC2 Clock Control
      //! PSC2 Clock Control
      //! @{

         //! @defgroup PSC2_clock_selection PSC2 Clock Selection
         //! PSC2 Clock Selection
         //! @{
//! Connect the PSC2 input clock to the PLL
#define Psc2_use_pll_clock()                          (PCNF2 |= (1<<PCLKSEL0) )
//! Connect the PSC2 input clock to the I/O clock
#define Psc2_use_io_clock()                           (PCNF2 &= ~(1<<PCLKSEL0) )
//! Start the PLL at 64MHz and connect it to PSC2
#define Psc2_use_64_mega_pll_clock()                                          \
          (Start_pll_64_mega(),                                               \
           Wait_pll_ready(),                                                  \
           Psc2_use_pll_clock() )
//! Start the PLL at 32MHz and connect it to PSC2
#define Psc2_use_32_mega_pll_clock()                                          \
          (Start_pll_32_mega(),                                               \
           Wait_pll_ready(),                                                  \
           Psc2_use_pll_clock() )
         //! @}

         //! @defgroup PSC2_prescaler_control PSC2 Prescaler Control
         //! PSC2 Prescaler Control
         //! @{
//! No PSC2prescaler
#define Disable_psc2_prescaler()                                              \
           (PCTL2 &= ~(  (1<<PPRE21) | (1<<PPRE20) ) )
//! PSC2 clock is internally divided by 4
#define Divide_psc2_input_clock_by_4()                                        \
           (PCTL2 &= ~(1<<PPRE21),                                            \
            PCTL2 |=  (1<<PPRE20) )
//! PSC2 clock is internally divided by 16
#define Divide_psc2_input_clock_by_16()                                       \
           (PCTL2 |=  (1<<PPRE21),                                            \
            PCTL2 &= ~(1<<PPRE20) )
//! PSC2 clock is internally divided by 64
#define Divide_psc2_input_clock_by_64()                                       \
           (PCTL2 |=  ((1<<PPRE21) | (1<<PPRE20)) )
         //! @}

      //! @}

      //! @defgroup PSC2_ramp_mode_selection PSC2 Ramp Mode Selection
      //! PSC2 Ramp Mode Selection
      //! @{
      //! PSC2 is configured in one ramp mode, it means that the internal counter
      //! counts from 0 up to OCR2RB
#define Psc2_in_1_ramp_mode()                                                 \
           (PCNF2 &= ~(  (1<<PMODE21) | (1<<PMODE20) ) )
//! PSC2 is configured in two ramp mode, it means that the internal counter
//! counts from 0 up to OCR2RA then from 0 to OCR2RB
#define Psc2_in_2_ramps_mode()                                                \
           (PCNF2 &= ~(1<<PMODE21),                                           \
            PCNF2 |=  (1<<PMODE20) )
//! PSC2 is configured in for ramp mode, it means that the internal counter
//! counts from 0 up to OCR2SA then from 0 to OCR2RA then from 0 to OCR2SB then from 0 to OCR2RB
#define Psc2_in_4_ramps_mode()                                                \
           (PCNF2 |=  (1<<PMODE21),                                           \
            PCNF2 &= ~(1<<PMODE20) )
//! PSC2 is configured in for ramp mode, it means that the internal counter
//! counts from 0 up to OCR2RB then from OCR2RB downto 0
#define Psc2_in_centered_aligned_mode()                                       \
           (PCNF2 |=  (  (1<<PMODE21) | (1<<PMODE20) ) )
      //! @}

      //! @defgroup PSC2_flank_width_modulation_configuration PSC2 Flank Width Modulation Configuration
      //! Select PSC2 Flank Width Modulation Configuration
      //! @{
#define Psc2_symetrical_flank_width_modulation()      (PCTL2 |=  (1<<PBFM2) )     //!< PSC2 Flank width modulation operates on both OCR2RA and OCR2RB
#define Psc2_end_of_cycle_flank_width_modulation()    (PCTL2 &= ~(1<<PBFM2) )     //!< PSC2 Flank width modulation operates only on OCR2RB
      //! @}

      //! @defgroup PSC2_adc_amplifier_trigger_configuration PSC2 ADC Amplifier Trigger Configuration
      //! Select the PSC2 trigger configuration for the ADC or the amplifier
      //! @{
//! The PSC2 synchronization signal is sent to the ADC/Amplifier on waveform generator A leading edge
#define Psc2_synchro_on_waveform_generator_a_leading_edge()                   \
           (PSCO2  &= ~(  (1<<PSYNC21) | (1<<PSYNC20) ) )
//! The PSC2 synchronization signal is sent to the ADC/Amplifier on waveform generator A trailing edge
#define Psc2_synchro_on_waveform_generator_a_trailing_edge()                  \
           (PSCO2 &= ~(1<<PSYNC21),                                           \
            PSCO2 |=  (1<<PSYNC20) )
//! The PSC2 synchronization signal is sent to the ADC/Amplifier on waveform generator B leading edge
#define Psc2_synchro_on_waveform_generator_b_leading_edge()                   \
           (PSCO2 |=  (1<<PSYNC21),                                           \
            PSCO2 &= ~(1<<PSYNC20) )
//! The PSC2 synchronization signal is sent to the ADC/Amplifier on waveform generator B trailing edge
#define Psc2_synchro_on_waveform_generator_b_trailing_edge()                  \
           (PSCO2 |=  (  (1<<PSYNC21) | (1<<PSYNC20) ) )
      //! @}

      //! @defgroup PSC2_run_control PSC2 Run Control
      //! Turn On and Off the PSC2
      //! @{
#define Start_psc2()                                  (PCTL2 |=  (1<<PRUN2) )     //!< Turn On PSC2
#define Stop_psc2()                                   (PCTL2 &= ~(1<<PRUN2) )     //!< Turn Off PSC2
//! Turn Off PSC2 and the end of cycle
#define Psc2_complete_waveform_and_stop()             (PCTL2 |=  (1<<PCCYC2), \
                                                       PCTL2 &= ~(1<<PRUN2) )
#define Is_psc2_started()                             (PCTL2 & (1<<PRUN2) )
      //! @}

      //! @defgroup PSC2_fault_mode_configuration PSC2 Fault Mode Configuration
      //! PSC2 Fault Mode Configuration
      //! @{
#define Enable_pscout20_fault_mode()                  (PCTL2 |=  (1<<PAOC2A) )    //!< Fault input select to block A can act directly to PSCOUT00 output
#define Disable_pscout20_fault_mode()                 (PCTL2 &= ~(1<<PAOC2A) )    //!< No fault or retrigger management on PSCOUT00

#define Enable_pscout21_fault_mode()                  (PCTL2 |=  (1<<PAOC2B) )    //!< Fault input select to block A can act directly to PSCOUT00 output
#define Disable_pscout21_fault_mode()                 (PCTL2 &= ~(1<<PAOC2B) )    //!< No fault or retrigger management on PSCOUT01

#define Enable_psc2_autorun()                         (PCTL2 |=  (1<<PARUN2) )    //!< Setting PRUN1 in PCTL1 register or setting both PARUN1 in PCTL1 register and PRUN0 in PCTL0 register will make the two PSC start simultaneously
#define Disable_psc2_autorun()                        (PCTL2 &= ~(1<<PARUN2) )    //!< No synchronization between PSC2 and PSC2 exists
      //! @}

      //! @defgroup PSC2_interrupt_configuration PSC2 Interrupt Configuration
      //! PSC2 interrupt configuration
      //! @{
#define Enable_psc2_synchro_error_interrupt()         (PIM2 |=  (1<<PSEIE2) )     //!< An interrupt is generated when the PSEI0 bit is set
#define Disable_psc2_synchro_error_interrupt()        (PIM2 &= ~(1<<PSEIE2) )     //!< No interrupt is generated when the PSEI0 bit is set

#define Enable_psc2_external_event_a_interrupt()      (PIM2 |=  (1<<PEVE2A) )     //!< An external event which can generate a capture from retrigger/fault block A generates an interrupt
#define Disable_psc2_external_event_a_interrupt()     (PIM2 &= ~(1<<PEVE2A) )     //!< An external event which can generate a capture from retrigger/fault block A doesn't generate any interrupt

#define Enable_psc2_external_event_b_interrupt()      (PIM2 |=  (1<<PEVE2B) )     //!< An external event which can generate a capture from retrigger/fault block B generates an interrupt
#define Disable_psc2_external_event_b_interrupt()     (PIM2 &= ~(1<<PEVE2B) )     //!< An external event which can generate a capture from retrigger/fault block B doesn't generate any interrupt

#define Enable_psc2_end_of_cycle_interrupt()          (PIM2 |=  (1<<PEVE2A) )     //!< An interrupt is generated when PSC2 reaches the end of the whole cycle
#define Disable_psc2_end_of_cycle_interrupt()         (PIM2 &= ~(1<<PEVE2A) )     //!< No interrupt is generated when PSC2 reaches the end of the whole cycle
      //! @}

      //! @defgroup PSC2_interrupt_flag_control PSC2 Interrupt Flag Control
      //! PSC2 interrupt flag control
      //! @{
#define Is_psc2_synchro_error_interrupt_flag_set()    (PIFR2 & (1<<PSEI0) )       //!< Return 1 if the PSEI0 bit in PIFR2 is set
#define Clear_psc2_synchro_error_interrupt_flag()     (PIFR2 &= ~(1<<PSEI0) )     //!< Clear PSEI0 bit in PIFR2 register

#define Is_psc2_external_event_a_interrupt_flag_set() (PIFR2 & (1<<PEV0A) )       //!< Return 1 if the PEV0A bit in PIFR2 is set
#define Clear_psc2_external_event_a_interrupt_flag()  (PIFR2 &= ~(1<<PEV0A) )     //!< Clear PEV0A bit in PIFR2 register

#define Is_psc2_external_event_b_interrupt_flag_set() (PIFR2 & (1<<PEV0B) )       //!< Return 1 if the PEV0B bit in PIFR2 is set
#define Clear_psc2_external_event_b_interrupt_flag()  (PIFR2 &= ~(1<<PEV0B) )     //!< Clear PEV0B bit in PIFR2 register

#define Is_psc2_end_of_cycle_interrupt_flag_set()     (PIFR2 & (1<<PEOP2) )       //!< Return 1 if the PE2P2 bit in PIFR2 is set
#define Clear_psc2_end_of_cycle_interrupt_flag()           (PIFR2 &= ~(1<<PEOP2) )     //!< Clear PEOP2 bit in PIFR2 register
      //! @}

      //! @defgroup PSC2_comparison_value_initilization PSC2 Comparison Value Initialization
      //! This section allows to fully initilaize the comprison values
      //! @{
//! Init all PSC2 comparison values
#define Init_psc2_all_compare_values(PSC2_DEADTIME0, PSC2_ONTIME0, PSC2_DEADTIME1, PSC2_ONTIME1)  \
           (OCR2SAH = HIGH((U16)PSC2_DEADTIME0),                              \
            OCR2SAL = LOW ((U16)PSC2_DEADTIME0),                              \
            OCR2RAH = HIGH((U16)PSC2_ONTIME0),                                \
            OCR2RAL = LOW ((U16)PSC2_ONTIME0),                                \
            OCR2SBH = HIGH((U16)PSC2_DEADTIME1),                              \
            OCR2SBL = LOW ((U16)PSC2_DEADTIME1),                              \
            OCR2RBH = HIGH((U16)PSC2_ONTIME1),                                \
            OCR2RBL = LOW ((U16)PSC2_ONTIME1)   )
//! Init PSC2 fifty percent comparison values (usefull for 50% mode)
#define Init_psc2_fifty_percent_compare_values(PSC2_DEADTIME1,PSC2_ONTIME1)              \
           (OCR2SBH = HIGH((U16)PSC2_DEADTIME1),                              \
            OCR2SBL = LOW ((U16)PSC2_DEADTIME1),                              \
            OCR2RBH = HIGH((U16)PSC2_ONTIME1),                                \
            OCR2RBL = LOW ((U16)PSC2_ONTIME1)   )
   //! @}


//_____ D E F I N I T I O N S ______________________________________________
   //! @defgroup PSC_structure_definitions PSC Structure Definitions
   //! These definitions shall be used by the PSC functions
   //! @{
typedef struct st_psc_comparison_values {
   U16 deadtime0;
   U16 ontime0;
   U16 deadtime1;
   U16 ontime1;
}Psc_comparison_values;

typedef struct st_psc_fifty_percent_comparison_values {
   U16 deadtime1;
   U16 ontime1;
}Psc_fifty_percent_comparison_values;
   //! @}

//_____ F U N C T I O N S __________________________________________________
   //! @defgroup PSC0_low_level_functions PSC0 Low Level Fucntions
   //! This section allows to fully configure the PSC0 mode and to start it with the wanted Comparison values
   //! @{
//! Configures the PSC0 accordingly to the PSC0 Define Configuration values,
//! Then Init the PSC0 comparison values and start it
void init_psc0         (void);
//! Update all the PSC0 comparison values accordingly to the four values
//! passed as U16 parameters
void update_psc0       ( Psc_comparison_values *psc0_comparison_values );
//! Update half the PSC0 comparison values accordingly to the two values
//! passed as U16 parameters
void update_psc0_fifty ( Psc_fifty_percent_comparison_values *psc0_fifty_percent_comparison_values );
   //! @}

   //! @defgroup PSC1_low_level_functions PSC1 Low Level Fucntions
   //! This section allows to fully configure the PSC1 mode and to start it with the wanted Comparison values
   //! @{
//! Configures the PSC1 accordingly to the PSC1 Define Configuration values,
//! Then Init the PSC1 comparison values and start it
void init_psc1         (void);
//! Update all the PSC1 comparison values accordingly to the four values
//! passed as U16 parameters
void update_psc1       ( Psc_comparison_values *psc1_comparison_values );
//! Update half the PSC1 comparison values accordingly to the two values
//! passed as U16 parameters
void update_psc1_fifty ( Psc_fifty_percent_comparison_values *psc1_fifty_percent_comparison_values );
   //! @}

   //! @defgroup PSC2_low_level_functions PSC2 Low Level Fucntions
   //! This section allows to fully configure the PSC2 mode and to start it with the wanted Comparison values
   //! @{
//! Configures the PSC2 accordingly to the PSC2 Define Configuration values,
//! Then Init the PSC2 comparison values and start it
void init_psc2         (void);
//! Update all the PSC2 comparison values accordingly to the four values
//! passed as U16 parameters
void update_psc2       ( Psc_comparison_values *psc2_comparison_values );
//! Update half the PSC2 comparison values accordingly to the two values
//! passed as U16 parameters
void update_psc2_fifty ( Psc_fifty_percent_comparison_values *psc2_fifty_percent_comparison_values );
   //! @}

//! @}
#endif  // PSC_DRV_H