psc_drv.h

DSP, 三相交流异步电机控制程序, C语言, 空间矢量SPWM, 内含PI算法及三相桥开关控制

      //! @defgroup PSC1_output_configuration PSC1 Output Configuration
      //! Select the PSC1 Outputs
      //! @{
#define Enable_pscout10()                             (PSOC1 |=  (1<<POEN1A) )  //!< Enable PSC1 Waveform Generator A
#define Disable_pscout10()                            (PSOC1 &= ~(1<<POEN1A) )  //!< Disable PSC1 Waveform Generator A

#define Enable_pscout11()                             (PSOC1 |=  (1<<POEN1B) )  //!< Enable PSC1 Waveform Generator B
#define Disable_pscout11()                            (PSOC1 &= ~(1<<POEN1B) )  //!< Disable PSC1 Waveform Generator B
//! Enable Both PSC1 Waveform Generator A and B
#define Enable_both_psc1_outputs()                                            \
           (PSOC1 |=  ((1<<POEN1A) | (1<<POEN1B)))
//! Disable Both PSC1 Waveform Generator A and B
#define Disable_both_psc1_outputs()                                           \
           (PSOC1 &= ~((1<<POEN1A) | (1<<POEN1B)))

#define Psc1_outputs_active_high()                    (PCNF1 |=  (1<<POP1) )    //!< PSC1 outputs are active low
#define Psc1_outputs_active_low()                     (PCNF1 &= ~(1<<POP1) )    //!< PSC1 outputs are active high
      //! @}

      //! @defgroup PSC1_mode_control_module PSC1 Mode Control
      //! PSC1 Mode Control
      //! @{
#define Enable_psc1_fifty_percent_mode()              (PCNF1 |=  (1<<PFIFTY1) )  //!< PSC1 is in 50% mode: Only OCR1RBH/L and OCR1SBH/L are used. They are duplicated in OCR1R/SAH/L during the update of OCR1BH/L
#define Disable_psc1_fifty_percent_mode()             (PCNF1 &= ~(1<<PFIFTY1) )  //!< OCR1R/SAH/L and OCR1R/SBH/L are fully independant

#define Enable_psc1_autolock_mode()                   (PCNF1 |=  (1<<PALOCK1) )  //!< OCR1R/SAH/L and OCR1R/SBH/L can be written without disturbing the PSC cycle. The update of these registers will be proceed at the end of the PSC cycle if the OCR1RB has been last written
#define Disable_psc1_autolock_mode()                  (PCNF1 &= ~(1<<PALOCK1) )  //!< The update will be procced according to PLOCK1 bit

#define Lock_psc1_compare_values()                    (PCNF1 |=  (1<<PLOCK1) )   //!< Take care that the lock is active only if you have disabled the autolock mode
#define Update_psc1_compare_values()                  (PCNF1 &= ~(1<<PLOCK1) )   //!< The compare registers will be updated with the content of OCR1AH/L and OCR1BH
      //! @}

      //! @defgroup PSC1_clock_control PSC1 Clock Control
      //! PSC1 Clock Control
      //! @{

         //! @defgroup PSC1_clock_selection PSC1 Clock Selection
         //! PSC1 Clock Selection
         //! @{
//! Connect the PSC1 input clock to the PLL
#define Psc1_use_pll_clock()                          (PCNF1 |= (1<<PCLKSEL0) )
//! Connect the PSC1 input clock to the I/O clock
#define Psc1_use_io_clock()                           (PCNF1 &= ~(1<<PCLKSEL0) )
//! Start the PLL at 64MHz and connect it to PSC1
#define Psc1_use_64_mega_pll_clock()                                          \
          (Start_pll_64_mega(),                                               \
           Wait_pll_ready(),                                                  \
           Psc1_use_pll_clock() )
//! Start the PLL at 32MHz and connect it to PSC1
#define Psc1_use_32_mega_pll_clock()                                          \
          (Start_pll_32_mega(),                                               \
           Wait_pll_ready(),                                                  \
           Psc1_use_pll_clock() )
         //! @}

         //! @defgroup PSC1_prescaler_control PSC1 Prescaler Control
         //! PSC1 Prescaler Control
         //! @{
//! No PSC1prescaler
#define Disable_psc1_prescaler()                                              \
           (PCTL1 &= ~(  (1<<PPRE11) | (1<<PPRE10) ) )
//! PSC1 clock is internally divided by 4
#define Divide_psc1_input_clock_by_4()                                        \
           (PCTL1 &= ~(1<<PPRE11),                                            \
            PCTL1 |=  (1<<PPRE10) )
//! PSC1 clock is internally divided by 16
#define Divide_psc1_input_clock_by_16()                                       \
           (PCTL1 |=  (1<<PPRE11),                                            \
            PCTL1 &= ~(1<<PPRE10) )
//! PSC1 clock is internally divided by 64
#define Divide_psc1_input_clock_by_64()                                       \
           (PCTL1 |=  ((1<<PPRE11) | (1<<PPRE10)) )
         //! @}

      //! @}

      //! @defgroup PSC1_ramp_mode_selection PSC1 Ramp Mode Selection
      //! PSC1 Ramp Mode Selection
      //! @{
      //! PSC1 is configured in one ramp mode, it means that the internal counter
      //! counts from 0 up to OCR1RB
#define Psc1_in_1_ramp_mode()                                                 \
           (PCNF1 &= ~(  (1<<PMODE11) | (1<<PMODE10) ) )
//! PSC1 is configured in two ramp mode, it means that the internal counter
//! counts from 0 up to OCR1RA then from 0 to OCR1RB
#define Psc1_in_2_ramps_mode()                                                \
           (PCNF1 &= ~(1<<PMODE11),                                           \
            PCNF1 |=  (1<<PMODE10) )
//! PSC1 is configured in for ramp mode, it means that the internal counter
//! counts from 0 up to OCR1SA then from 0 to OCR1RA then from 0 to OCR1SB then from 0 to OCR1RB
#define Psc1_in_4_ramps_mode()                                                \
           (PCNF1 |=  (1<<PMODE11),                                           \
            PCNF1 &= ~(1<<PMODE10) )
//! PSC1 is configured in for ramp mode, it means that the internal counter
//! counts from 0 up to OCR1RB then from OCR1RB downto 0
#define Psc1_in_centered_aligned_mode()                                       \
           (PCNF1 |=  (  (1<<PMODE11) | (1<<PMODE10) ) )
      //! @}

      //! @defgroup PSC1_flank_width_modulation_configuration PSC1 Flank Width Modulation Configuration
      //! Select PSC1 Flank Width Modulation Configuration
      //! @{
#define Psc1_symetrical_flank_width_modulation()      (PCTL1 |=  (1<<PBFM1) )     //!< PSC1 Flank width modulation operates on both OCR1RA and OCR1RB
#define Psc1_end_of_cycle_flank_width_modulation()    (PCTL1 &= ~(1<<PBFM1) )     //!< PSC1 Flank width modulation operates only on OCR1RB
      //! @}

      //! @defgroup PSC1_adc_amplifier_trigger_configuration PSC1 ADC Amplifier Trigger Configuration
      //! Select the PSC1 trigger configuration for the ADC or the amplifier
      //! @{
//! The PSC1 synchronization signal is sent to the ADC/Amplifier on waveform generator A leading edge
#define Psc1_synchro_on_waveform_generator_a_leading_edge()                   \
           (PSCO1 &= ~(  (1<<PSYNC11) | (1<<PSYNC10) ) )
//! The PSC1 synchronization signal is sent to the ADC/Amplifier on waveform generator A trailing edge
#define Psc1_synchro_on_waveform_generator_a_trailing_edge()                  \
           (PSCO1 &= ~(1<<PSYNC11),                                           \
            PSCO1 |=  (1<<PSYNC10) )
//! The PSC1 synchronization signal is sent to the ADC/Amplifier on waveform generator B leading edge
#define Psc1_synchro_on_waveform_generator_b_leading_edge()                   \
           (PSCO1 |=  (1<<PSYNC11),                                           \
            PSCO1 &= ~(1<<PSYNC10) )
//! The PSC1 synchronization signal is sent to the ADC/Amplifier on waveform generator B trailing edge
#define Psc1_synchro_on_waveform_generator_b_trailing_edge()                  \
           (PSCO1 |=  (  (1<<PSYNC11) | (1<<PSYNC10) ) )
      //! @}

      //! @defgroup PSC1_run_control PSC1 Run Control
      //! Turn On and Off the PSC1
      //! @{
#define Start_psc1()                                  (PCTL1 |=  (1<<PRUN1) )     //!< Turn On PSC1
#define Stop_psc1()                                   (PCTL1 &= ~(1<<PRUN1) )     //!< Turn Off PSC1
//! Turn Off PSC1 and the end of cycle
#define Psc1_complete_waveform_and_stop()             (PCTL1 |=  (1<<PCCYC1), \
                                                       PCTL1 &= ~(1<<PRUN1) )
#define Is_psc1_started()                             (PCTL1 & (1<<PRUN1) )
      //! @}

      //! @defgroup PSC1_fault_mode_configuration PSC1 Fault Mode Configuration
      //! PSC1 Fault Mode Configuration
      //! @{
#define Enable_pscout10_fault_mode()                  (PCTL1 |=  (1<<PAOC1A) )    //!< Fault input select to block A can act directly to PSCOUT00 output
#define Disable_pscout10_fault_mode()                 (PCTL1 &= ~(1<<PAOC1A) )    //!< No fault or retrigger management on PSCOUT00

#define Enable_pscout11_fault_mode()                  (PCTL1 |=  (1<<PAOC1B) )    //!< Fault input select to block A can act directly to PSCOUT00 output
#define Disable_pscout11_fault_mode()                 (PCTL1 &= ~(1<<PAOC1B) )    //!< No fault or retrigger management on PSCOUT01

#define Enable_psc1_autorun()                         (PCTL1 |=  (1<<PARUN1) )    //!< Setting PRUN0 in PCTL0 register or setting both PARUN0 in PCTL0 register and PRUN2 in PCTL2 register will make the two PSC start simultaneously
#define Disable_psc1_autorun()                        (PCTL1 &= ~(1<<PARUN1) )    //!< No synchronization between PSC2 and PSC1 exists
      //! @}

      //! @defgroup PSC1_interrupt_configuration PSC1 Interrupt Configuration
      //! PSC1 interrupt configuration
      //! @{
#define Enable_psc1_synchro_error_interrupt()         (PIM1 |=  (1<<PSEIE1) )     //!< An interrupt is generated when the PSEI0 bit is set
#define Disable_psc1_synchro_error_interrupt()        (PIM1 &= ~(1<<PSEIE1) )     //!< No interrupt is generated when the PSEI0 bit is set

#define Enable_psc1_external_event_a_interrupt()      (PIM1 |=  (1<<PEVE1A) )     //!< An external event which can generate a capture from retrigger/fault block A generates an interrupt
#define Disable_psc1_external_event_a_interrupt()     (PIM1 &= ~(1<<PEVE1A) )     //!< An external event which can generate a capture from retrigger/fault block A doesn't generate any interrupt

#define Enable_psc1_external_event_b_interrupt()      (PIM1 |=  (1<<PEVE1B) )     //!< An external event which can generate a capture from retrigger/fault block B generates an interrupt
#define Disable_psc1_external_event_b_interrupt()     (PIM1 &= ~(1<<PEVE1B) )     //!< An external event which can generate a capture from retrigger/fault block B doesn't generate any interrupt

#define Enable_psc1_end_of_cycle_interrupt()          (PIM1 |=  (1<<PEVE1A) )     //!< An interrupt is generated when PSC1 reaches the end of the whole cycle
#define Disable_psc1_end_of_cycle_interrupt()         (PIM1 &= ~(1<<PEVE1A) )     //!< No interrupt is generated when PSC1 reaches the end of the whole cycle
      //! @}

      //! @defgroup PSC1_interrupt_flag_control PSC1 Interrupt Flag Control
      //! PSC1 interrupt flag control
      //! @{
#define Is_psc1_synchro_error_interrupt_flag_set()    (PIFR1 & (1<<PSEI0) )       //!< Return 1 if the PSEI0 bit in PIFR1 is set
#define Clear_psc1_synchro_error_interrupt_flag()     (PIFR1 &= ~(1<<PSEI0) )     //!< Clear PSEI0 bit in PIFR1 register

#define Is_psc1_external_event_a_interrupt_flag_set() (PIFR1 & (1<<PEV0A) )       //!< Return 1 if the PEV0A bit in PIFR1 is set
#define Clear_psc1_external_event_a_interrupt_flag()  (PIFR1 &= ~(1<<PEV0A) )     //!< Clear PEV0A bit in PIFR1 register

#define Is_psc1_external_event_b_interrupt_flag_set() (PIFR1 & (1<<PEV0B) )       //!< Return 1 if the PEV0B bit in PIFR1 is set
#define Clear_psc1_external_event_b_interrupt_flag()  (PIFR1 &= ~(1<<PEV0B) )     //!< Clear PEV0B bit in PIFR1 register

#define Is_psc1_end_of_cycle_interrupt_flag_set()     (PIFR1 & (1<<PEOP1) )       //!< Return 1 if the PEOP1 bit in PIFR1 is set
#define Clear_psc1_end_of_cycle_interrupt_flag()      (PIFR1 &= ~(1<<PEOP1) )     //!< Clear PEOP1 bit in PIFR1 register
      //! @}

      //! @defgroup PSC1_comparison_value_initilization PSC1 Comparison Value Initialization
      //! This section allows to fully initilaize the comprison values
      //! @{
//! Init all PSC1 comparison values
#define Init_psc1_all_compare_values(PSC1_DEADTIME0, PSC1_ONTIME0, PSC1_DEADTIME1, PSC1_ONTIME1)  \
           (OCR1SAH = HIGH((U16)PSC1_DEADTIME0),                              \
            OCR1SAL = LOW ((U16)PSC1_DEADTIME0),                              \
            OCR1RAH = HIGH((U16)PSC1_ONTIME0),                                \
            OCR1RAL = LOW ((U16)PSC1_ONTIME0),                                \
            OCR1SBH = HIGH((U16)PSC1_DEADTIME1),                              \
            OCR1SBL = LOW ((U16)PSC1_DEADTIME1),                              \
            OCR1RBH = HIGH((U16)PSC1_ONTIME1),                                \
            OCR1RBL = LOW ((U16)PSC1_ONTIME1)   )
//! Init PSC1 fifty percent comparison values (usefull for 50% mode)
#define Init_psc1_fifty_percent_compare_values(PSC1_DEADTIME1, PSC1_ONTIME1)              \
           (OCR1SBH = HIGH((U16)PSC1_DEADTIME1),                              \
            OCR1SBL = LOW ((U16)PSC1_DEADTIME1),                              \
            OCR1RBH = HIGH((U16)PSC1_ONTIME1),                                \
            OCR1RBL = LOW ((U16)PSC1_ONTIME1)   )
      //! @}
   //! @}


   //! @defgroup PSC2_macros PSC2 Macros
   //! PSC2 Macros
   //! @{

      //! @defgroup PSC2_output_configuration PSC2 Output Configuration
      //! Select the PSC2 Outputs
      //! @{
#define Enable_pscout20()                             (PSOC2 |=  (1<<POEN2A) )  //!< Enable PSC2 Waveform Generator A
#define Disable_pscout20()                            (PSOC2 &= ~(1<<POEN2A) )  //!< Disable PSC2 Waveform Generator A

#define Enable_pscout21()                             (PSOC2 |=  (1<<POEN2B) )  //!< Enable PSC2 Waveform Generator B
#define Disable_pscout21()                            (PSOC2 &= ~(1<<POEN2B) )  //!< Disable PSC2 Waveform Generator B
//! Enable Both PSC2 Waveform Generator A and B
#define Enable_both_psc2_outputs()                                            \
           (PSOC2 |=  ((1<<POEN2A) | (1<<POEN2B)))
//! Disable Both PSC2 Waveform Generator A and B
#define Disable_both_psc2_outputs()                                           \
           (PSOC2 &= ~((1<<POEN2A) | (1<<POEN2B)))

#define Psc2_outputs_active_high()                    (PCNF2 |=  (1<<POP2) )    //!< PSC2 outputs are active low
#define Psc2_outputs_active_low()                     (PCNF2 &= ~(1<<POP2) )    //!< PSC2 outputs are active high
      //! @}

      //! @defgroup PSC2_mode_control_module PSC2 Mode Control
      //! PSC2 Mode Control
      //! @{
#define Enable_psc2_fifty_percent_mode()              (PCNF2 |=  (1<<PFIFTY2) )  //!< PSC2 is in 50% mode: Only OCR2RBH/L and OCR2SBH/L are used. They are duplicated in OCR2R/SAH/L during the update of OCR2BH/L
#define Disable_psc2_fifty_percent_mode()             (PCNF2 &= ~(1<<PFIFTY2) )  //!< OCR2R/SAH/L and OCR2R/SBH/L are fully independant

#define Enable_psc2_autolock_mode()                   (PCNF2 |=  (1<<PALOCK2) )  //!< OCR2R/SAH/L and OCR2R/SBH/L can be written without disturbing the PSC cycle. The update of these registers will be proceed at the end of the PSC cycle if the OCR2RB has been last written
#define Disable_psc2_autolock_mode()                  (PCNF2 &= ~(1<<PALOCK2) )  //!< The update will be procced according to PLOCK2 bit

#define Lock_psc2_compare_values()                    (PCNF2 |=  (1<<PLOCK2) )   //!< Take care that the lock is active only if you have disabled the autolock mode
#define Update_psc2_compare_values()                  (PCNF2 &= ~(1<<PLOCK2) )   //!< The compare registers will be updated with the content of OCR2AH/L and OCR2BH