spmc70_regs.inc

基于SPMC75的NNAD_Flash K9F1208的驱动程式序,对一些需要存海量数据的单片机应用场合有用.

// ========================================================================= //
// File Name   : Spmc70_regs.inc									     	 //	
// Description : SPMC70 series register definition						     //
// Processor   : SPMC701FM0A												 //	
// Author      : Sunplus SA7											     //
// Date        : Jun 2004											     	 //
// Tools	   : u'nSP IDE tools v1.15.x									 //
// Version     : 2.00 													     //	
// Security    : Confidential Proprietary 							         //
// Updata	   : 2004/7/6													 //
// 			   : 2nd Version												 //
// ========================================================================= //

//***************************************************************************//
// A. CPU control register													 //
//***************************************************************************//
.DEFINE P_Clk_Ctrl				0x7069
.DEFINE P_System_Option			0x8000			
.DEFINE P_WatchDog_Ctrl			0x7063
.DEFINE P_WatchDog_Clr			0x7064
.DEFINE P_Reset_Status			0x7065

//***************************************************************************//
// B. Flash organization and control register								 //
//***************************************************************************//
.DEFINE P_Flash_RW				0x7068	
.DEFINE P_Flash_Ctrl			0x7555
.DEFINE P_Wait_State			0x706C

//***************************************************************************//
// C. Interrupt control register											 // 	
//***************************************************************************//
.DEFINE P_INT_Ctrl				0x7060
.DEFINE P_INT_Priority			0x7061
.DEFINE P_INT_Status			0x7062
.DEFINE P_TimeBase_Setup		0x7040
.DEFINE P_TimeBase_Clr			0x7041

//***************************************************************************//
// D. I/O Port register														 //
//***************************************************************************//
.DEFINE P_IOA_Data				0x7000
.DEFINE P_IOA_Buffer			0x7001
.DEFINE P_IOA_Dir				0x7002
.DEFINE P_IOA_Attrib			0x7003
.DEFINE P_IOA_Latch				0x7004

.DEFINE P_IOB_Data				0x7008
.DEFINE P_IOB_Buffer			0x7009
.DEFINE P_IOB_Dir				0x700A
.DEFINE P_IOB_Attrib			0x700B
.DEFINE P_IOB_Latch				0x700C

.DEFINE P_IOC_Data				0x7010
.DEFINE P_IOC_Buffer			0x7011
.DEFINE P_IOC_Dir				0x7012
.DEFINE P_IOC_Attrib			0x7013
.DEFINE P_IOC_Latch				0x7014

.DEFINE P_IOD_Data				0x7018
.DEFINE P_IOD_Buffer			0x7019
.DEFINE P_IOD_Dir				0x701A
.DEFINE P_IOD_Attrib			0x701B
.DEFINE P_IOD_Latch				0x701C

//***************************************************************************//
// E. Low voltage reset and low voltage detection register					 //
//***************************************************************************//
.DEFINE P_LVDLVR_Ctrl			0x7066
.DEFINE P_LVD_Status			0x7067				

//***************************************************************************//
// F. Power saving modes and wakeup register								 //
//***************************************************************************//
.DEFINE P_Wakeup_Source			0x706A
.DEFINE P_Halt_Enter			0x706E
.DEFINE P_Stdby_Enter			0x706D
.DEFINE P_Wakeup_Status			0x706F
.DEFINE	P_Sleep_Enter			0x706B

//***************************************************************************//
// G. Parallel Communication Interface register								 //
//***************************************************************************//
.DEFINE P_PCI_Ctrl				0x70C0
.DEFINE P_PCI_Status			0x70C1
.DEFINE P_PCI_RxBuf				0x70C2
.DEFINE P_PCI_TxBuf				0x70C3
.DEFINE P_PCI_COMM				0x70C4			

//***************************************************************************//
// H. Timer 0, Timer 1, Timer 2												 //
//***************************************************************************//
.DEFINE P_Timer0_Ctrl			0x7044
.DEFINE P_Timer0_Preload		0x7045
.DEFINE P_Timer0_CCPR			0x7046
.DEFINE P_Timer0_CCPR2			0x7047

.DEFINE P_Timer1_Ctrl			0x7048
.DEFINE P_Timer1_Preload		0x7049
.DEFINE P_Timer1_CCPR			0x704A
.DEFINE P_Timer1_CCPR2			0x704B

.DEFINE P_Timer2_Ctrl			0x704C
.DEFINE P_Timer2_Preload		0x704D

//***************************************************************************//
// I. Standard Peripheral Interface SPI register							 //				
//***************************************************************************//
.DEFINE P_SPI_Ctrl				0x7090
.DEFINE P_SPI_Status			0x7091
.DEFINE P_SPI_TxBuf				0x7092
.DEFINE P_SPI_RxBuf				0x7092

//***************************************************************************//
// J. Serial input and output SIO register									 //	
//***************************************************************************//
.DEFINE P_SIO_Ctrl				0x70B0
.DEFINE P_SIO_Status			0x70B1
.DEFINE P_SIO_Buf				0x70B2
.DEFINE P_SIO_Addr				0x70B3

//***************************************************************************//
// K. Universal Asychronous Receiver/Transmitter UART register				 //
//***************************************************************************//
.DEFINE P_UART_Ctrl				0x70A0
.DEFINE P_UART_Status			0x70A1
.DEFINE P_UART_Reset			0x70A2
.DEFINE P_UART_BaudRateL		0x70A3
.DEFINE P_UART_BaudRateH		0x70A4
.DEFINE P_UART_TxBuf			0x70A5
.DEFINE P_UART_RxBuf			0x70A6

//***************************************************************************//
// L. 10-bit ADC converter register											 //
//***************************************************************************//
.DEFINE P_ADC_Ctrl				0x7070
.DEFINE P_ADC_Data				0x7071



//=================================//
// A. flash control register	   //
//=================================//
// P_System_Option register // 
// word set //
.DEFINE CW_SYS_CLK_R				0x0000
.DEFINE CW_SYS_CLK_OSC				0x0001

.DEFINE CW_SYS_WDG_Disable			0x0000
.DEFINE CW_SYS_WDG_Enable			(0x0001 << 1)

.DEFINE CW_SYS_LVR_Disable			0x0000 
.DEFINE CW_SYS_LVR_Enable			(0x0001 << 2)

.DEFINE CW_SYS_LVD_Disable			0x0000
.DEFINE CW_SYS_LVD_Enable			(0x0001 << 3)

.DEFINE CW_SYS_Security_Protect		0x0000 
.DEFINE CW_SYS_Security_NoProtect	(0x0001 << 4)

.DEFINE CW_SYS_Verification 		(0x02AA << 5)

// P_Flash_RW register //
// word set //
.DEFINE	CW_BK14WDIS					(0x0001 << 14)	//BANK 14 Write Disable
.DEFINE	CW_BK13WDIS					(0x0001 << 13)	//BANK 13 Write Disable
.DEFINE	CW_BK12WDIS					(0x0001 << 12)	//BANK 12 Write Disable
.DEFINE	CW_BK11WDIS					(0x0001 << 11)	//BANK 11 Write Disable
.DEFINE	CW_BK10WDIS					(0x0001 << 10)	//BANK 10 Write Disable
.DEFINE	CW_BK9WDIS					(0x0001 << 9)	//BANK 9 Write Disable
.DEFINE	CW_BK8WDIS					(0x0001 << 8)	//BANK 8 Write Disable
.DEFINE	CW_BK7WDIS					(0x0001 << 7)	//BANK 7 Write Disable
.DEFINE	CW_BK6WDIS					(0x0001 << 6)	//BANK 6 Write Disable
.DEFINE	CW_BK5WDIS					(0x0001 << 5)	//BANK 5 Write Disable
.DEFINE	CW_BK4WDIS					(0x0001 << 4)	//BANK 4 Write Disable
.DEFINE	CW_BK3WDIS					(0x0001 << 3)	//BANK 3 Write Disable
.DEFINE	CW_BK2WDIS					(0x0001 << 2)	//BANK 2 Write Disable
.DEFINE	CW_BK1WDIS					(0x0001 << 1)	//BANK 1 Write Disable
.DEFINE	CW_BK0WDIS					0x0001			//BANK 0 Write Disable


// P_Flash_Ctrl register //
// word set //
.DEFINE	CW_FlashRW_CMD				0x5A5A			//Flash RW Command
.DEFINE	CW_FlashCMD					0xAAAA			//Flash Command FLash Block
.DEFINE	CW_PageErase				0x5511			//Flash Page Erase Command
.DEFINE	CW_Program					0x5533			//Flash Program Command
.DEFINE	CW_Sequential				0x5544			//Flash Sequential Program Command
.DEFINE	CW_SequentialEnd			0xFFFF			//Flash Sequential Program End Command


// P_Wait_State register //
// word set //
.DEFINE	CW_WSCYCT_1					0x0001			//Wait Cycle 1
.DEFINE	CW_WSCYCT_2					0x0002			//Wait Cycle 2
.DEFINE	CW_WSCYCT_3					0x0003			//Wait Cycle 3
.DEFINE	CW_WSCYCT_4					0x0004			//Wait Cycle 4
.DEFINE	CW_WSCYCT_5					0x0005			//Wait Cycle 5
.DEFINE	CW_WSCYCT_6					0x0006			//Wait Cycle 6
.DEFINE	CW_WSCYCT_7					0x0007			//Wait Cycle 7
.DEFINE	CW_WSCYCT_8					0x0008			//Wait Cycle 8


//=================================//
// B. CPU control register		   //
//=================================//
// P_Clk_Ctrl register //
// word set //
.DEFINE	CW_Clk_CMD					0x5A5A			//Clock Setting Command
.DEFINE	CW_CLKSEL_24M				0x0000			//24M
.DEFINE	CW_CLKSEL_48M				0x0001			//48M
.DEFINE	CW_CLKSEL_12M				0x0002			//12M
.DEFINE	CW_CLKSEL_6M				0x0003			//6M
.DEFINE	CW_CLKSEL_3M				0x0004			//3M
.DEFINE	CW_CLKSEL_1500K				0x0005			//1.5M
.DEFINE	CW_CLKSEL_750K				0x0006			//750K
.DEFINE	CW_CLKSEL_32K				0x0007			//32K


// P_WatchDog_Ctrl register //
// word set //
.DEFINE CW_WDTTMR_RST_DISABLE		0x0001
.DEFINE CW_WDTTMR_SET_2683MS		(0x0007 << 1)
.DEFINE CW_WDTTMR_SET_1341MS		(0x0006 << 1)
.DEFINE CW_WDTTMR_SET_670MS			(0x0005 << 1)
.DEFINE CW_WDTTMR_SET_355MS			(0x0004 << 1)
.DEFINE CW_WDTTMR_SET_168MS			(0x0003 << 1)
.DEFINE CW_WDTTMR_SET_83840US		(0x0002 << 1)
.DEFINE CW_WDTTMR_SET_41920US		(0x0001 << 1)
.DEFINE CW_WDTTMR_SET_20960US		0x0000


// P_WatchDog_Clr register //
// word set //
.DEFINE 	CW_WDTCLR				0x5A5A			//Clear watchdog


// P_Reset_Status register //
// word set //
.DEFINE CW_CLEAR_PCIRST				(0x0001 << 5)
.DEFINE CW_CLEAR_ICERST				(0x0001 << 4)
.DEFINE CW_CLEAR_ILLADDR			(0x0001 << 3)
.DEFINE CW_CLEAR_WDTRST				(0x0001 << 2)
.DEFINE CW_CLEAR_LVRST				(0x0001 << 1)
.DEFINE CW_CLEAR_EXTRST				0x0001

//=================================//
// C. Interrupt control register   //
//=================================//
// P_INT_Ctrl register //
// word set //
.DEFINE CW_2HZ_INT_EN				0x0001 
.DEFINE CW_4HZ_INT_EN				(0x0001 << 1)
.DEFINE CW_TMB1_INT_EN				(0x0001 << 2)
.DEFINE CW_TMB2_INT_EN				(0x0001 << 3)
.DEFINE CW_KEY_INT_EN				(0x0001 << 4)
.DEFINE CW_EXT1_RISE_TRIGGER		(0x0001 << 5)
.DEFINE CW_EXT2_RISE_TRIGGER		(0x0001 << 6)
.DEFINE CW_EXT1_INT_EN				(0x0001 << 7)
.DEFINE CW_EXT2_INT_EN				(0x0001 << 8)
.DEFINE CW_EXT1PIN_INEN				(0x0001 << 9)
.DEFINE CW_EXT2PIN_INEN				(0x0001 << 10)


// P_INT_Priority register //
// word set //
.DEFINE CW_KEYIP_SET_FIQ			(0x0001 << 4)
.DEFINE CW_LVDIP_SET_FIQ			(0x0001 << 5)
.DEFINE CW_TMR0IP_SET_FIQ			(0x0001 << 6)
.DEFINE CW_TMR1IP_SET_FIQ			(0x0001 << 7)
.DEFINE CW_TMR2IP_SET_FIQ			(0x0001 << 8)
.DEFINE CW_PCIIP_SET_FIQ			(0x0001 << 9)
.DEFINE CW_SIOIP_SET_FIQ			(0x0001 << 10)
.DEFINE CW_SPIIP_SET_FIQ			(0x0001 << 11)
.DEFINE CW_UARTIP_SET_FIQ			(0x0001 << 12)
.DEFINE CW_EXT1IP_SET_FIQ			(0x0001 << 13)
.DEFINE CW_EXT2IP_SET_FIQ			(0x0001 << 14)
.DEFINE CW_ADCIP_SET_FIQ			(0x0001 << 15)


// P_INT_Status register //
// word set //
.DEFINE CW_CLEAR_2HZINTF			0x0001
.DEFINE CW_CLEAR_4HZINTF			(0x0001 << 1)
.DEFINE CW_CLEAR_TMB1INTF			(0x0001 << 2)
.DEFINE CW_CLEAR_TMB2INTF			(0x0001 << 3)
.DEFINE CW_CLEAR_KEYINTF			(0x0001 << 4)
.DEFINE CW_CLEAR_LVDINTF			(0x0001 << 5)
.DEFINE CW_CLEAR_TMR0INTF			(0x0001 << 6)
.DEFINE CW_CLEAR_TMR1INTF			(0x0001 << 7)
.DEFINE CW_CLEAR_TMR2INTF			(0x0001 << 8)
.DEFINE CW_CLEAR_PCIINTF			(0x0001 << 9)
.DEFINE CW_CLEAR_SIOINTF			(0x0001 << 10)
.DEFINE CW_CLEAR_SPIINTF			(0x0001 << 11)
.DEFINE CW_CLEAR_UARTINTF			(0x0001 << 12)
.DEFINE CW_CLEAR_EXT1INTF			(0x0001 << 13)
.DEFINE CW_CLEAR_EXT2INTF			(0x0001 << 14)
.DEFINE CW_CLEAR_ADCINTF			(0x0001 << 15)


// P_TimeBase_Setup register //
// word set //
.DEFINE	CW_TMBDefault			0x0000			//TMB default value
.DEFINE CW_TMBENB_ENABLE		0x0000			//Ensable TimeBase
.DEFINE CW_TMBENB_DISABLE		(0x0001 << 4)	//Disable TimeBase
.DEFINE CW_TMB1FS_8HZ			0x0000			//Set TimeBase1 as 8  HZ
.DEFINE CW_TMB1FS_16HZ			0x0001			//Set TimeBase1 as 16 HZ
.DEFINE CW_TMB1FS_32HZ			0x0002			//Set TimeBase1 as 32 HZ
.DEFINE CW_TMB1FS_64HZ			0x0003			//Set TimeBase1 as 64 HZ
.DEFINE CW_TMB2FS_128HZ			0x0000			//Set TimeBase2 as 128 HZ
.DEFINE CW_TMB2FS_256HZ			(0x0001 << 2)	//Set TimeBase2 as 256 HZ
.DEFINE CW_TMB2FS_512HZ			(0x0002 << 2)	//Set TimeBase2 as 512 HZ
.DEFINE CW_TMB2FS_1024HZ		(0x0003 << 2)	//Set TimeBase2 as 1024 HZ


// P_TimeBase_Clr register //
// word set //
.DEFINE 	CW_TMBCLR				0x5555			//Clear TimeBase


//=================================//
// D. I/O Port register			   //
//=================================//
// P_IOn_Dir register //					//n: is A,B,C,D
// word set //
.DEFINE CW_PORTPAD0_AS_OUTPUT		0x0001
.DEFINE CW_PORTPAD1_AS_OUTPUT		(0x0001 << 1)
.DEFINE CW_PORTPAD2_AS_OUTPUT		(0x0001 << 2)
.DEFINE CW_PORTPAD3_AS_OUTPUT		(0x0001 << 3)
.DEFINE CW_PORTPAD4_AS_OUTPUT		(0x0001 << 4)
.DEFINE CW_PORTPAD5_AS_OUTPUT		(0x0001 << 5)
.DEFINE CW_PORTPAD6_AS_OUTPUT		(0x0001 << 6)
.DEFINE CW_PORTPAD7_AS_OUTPUT		(0x0001 << 7)
.DEFINE CW_PORTPAD8_AS_OUTPUT		(0x0001 << 8)
.DEFINE CW_PORTPAD9_AS_OUTPUT		(0x0001 << 9)
.DEFINE CW_PORTPAD10_AS_OUTPUT		(0x0001 << 10)
.DEFINE CW_PORTPAD11_AS_OUTPUT		(0x0001 << 11)
.DEFINE CW_PORTPAD12_AS_OUTPUT		(0x0001 << 12)
.DEFINE CW_PORTPAD13_AS_OUTPUT		(0x0001 << 13)
.DEFINE CW_PORTPAD14_AS_OUTPUT		(0x0001 << 14)
.DEFINE CW_PORTPAD15_AS_OUTPUT		(0x0001 << 15)


// P_IOn_Attrib register //					//n: is A,B,C,D
// word set //
.DEFINE CW_PORTPAD0_NONINV			0x0001	
.DEFINE CW_PORTPAD1_NONINV			(0x0001 << 1)	
.DEFINE CW_PORTPAD2_NONINV			(0x0001 << 2)	
.DEFINE CW_PORTPAD3_NONINV			(0x0001 << 3)	
.DEFINE CW_PORTPAD4_NONINV			(0x0001 << 4)	
.DEFINE CW_PORTPAD5_NONINV			(0x0001 << 5)	
.DEFINE CW_PORTPAD6_NONINV			(0x0001 << 6)	
.DEFINE CW_PORTPAD7_NONINV			(0x0001 << 7)	
.DEFINE CW_PORTPAD8_NONINV			(0x0001 << 8)	
.DEFINE CW_PORTPAD9_NONINV			(0x0001 << 9)	
.DEFINE CW_PORTPAD10_NONINV			(0x0001 << 10)
.DEFINE CW_PORTPAD11_NONINV			(0x0001 << 11)
.DEFINE CW_PORTPAD12_NONINV			(0x0001 << 12)
.DEFINE CW_PORTPAD13_NONINV			(0x0001 << 13)
.DEFINE CW_PORTPAD14_NONINV			(0x0001 << 14)
.DEFINE CW_PORTPAD15_NONINV			(0x0001 << 15)

// P_IOn_Data/P_IOn_Buffer register //		//n: is A,B,C,D
// word set //
.DEFINE CW_PORTPAD0_SET_HI			0x0001
.DEFINE CW_PORTPAD1_SET_HI			(0x0001 << 1)
.DEFINE CW_PORTPAD2_SET_HI			(0x0001 << 2)
.DEFINE CW_PORTPAD3_SET_HI			(0x0001 << 3)
.DEFINE CW_PORTPAD4_SET_HI			(0x0001 << 4)