spmc70_regs.h

基于SPMC75的NNAD_Flash K9F1208的驱动程式序,对一些需要存海量数据的单片机应用场合有用.

#define	CW_WSCYCT_7					0x0007			//Wait Cycle 7
#define	CW_WSCYCT_8					0x0008			//Wait Cycle 8


/*=================================*/
/* B. CPU control register		   */
/*=================================*/
/* P_Clk_Ctrl register */
/* word set */
#define	CW_Clk_CMD					0x5A5A			//Clock Setting Command
#define	CW_CLKSEL_24M				0x0000			//24M
#define	CW_CLKSEL_48M				0x0001			//48M
#define	CW_CLKSEL_12M				0x0002			//12M
#define	CW_CLKSEL_6M				0x0003			//6M
#define	CW_CLKSEL_3M				0x0004			//3M
#define	CW_CLKSEL_1500K				0x0005			//1.5M
#define	CW_CLKSEL_750K				0x0006			//750K
#define	CW_CLKSEL_32K				0x0007			//32K


/* P_WatchDog_Ctrl register */
/* bit set */
#define CB_WDTTMR_RST_DISABLE		0x0001
#define CB_WDTTMR_SET_2683MS		0x0007
#define CB_WDTTMR_SET_1341MS		0x0006
#define CB_WDTTMR_SET_670MS			0x0005
#define CB_WDTTMR_SET_355MS			0x0004
#define CB_WDTTMR_SET_168MS			0x0003
#define CB_WDTTMR_SET_83840US		0x0002
#define CB_WDTTMR_SET_41920US		0x0001
#define CB_WDTTMR_SET_20960US		0x0000
/* word set */
#define CW_WDTTMR_RST_DISABLE		0x0001
#define CW_WDTTMR_SET_2683MS		(0x0007 << 1)
#define CW_WDTTMR_SET_1341MS		(0x0006 << 1)
#define CW_WDTTMR_SET_670MS			(0x0005 << 1)
#define CW_WDTTMR_SET_355MS			(0x0004 << 1)
#define CW_WDTTMR_SET_168MS			(0x0003 << 1)
#define CW_WDTTMR_SET_83840US		(0x0002 << 1)
#define CW_WDTTMR_SET_41920US		(0x0001 << 1)
#define CW_WDTTMR_SET_20960US		0x0000


/* P_WatchDog_Clr register */
/* word set */
#define 	CW_WDTCLR				0x5A5A			//Clear watchdog


/* P_Reset_Status register */
/* bit set */
#define CB_CLEAR_PCIRST				0x0001
#define CB_CLEAR_ICERST				0x0001
#define CB_CLEAR_ILLADDR			0x0001
#define CB_CLEAR_WDTRST				0x0001
#define CB_CLEAR_LVRST				0x0001
#define CB_CLEAR_EXTRST				0x0001
/* word set */
#define CW_CLEAR_PCIRST				(0x0001 << 5)
#define CW_CLEAR_ICERST				(0x0001 << 4)
#define CW_CLEAR_ILLADDR			(0x0001 << 3)
#define CW_CLEAR_WDTRST				(0x0001 << 2)
#define CW_CLEAR_LVRST				(0x0001 << 1)
#define CW_CLEAR_EXTRST				0x0001

/*=================================*/
/* C. Interrupt control register   */
/*=================================*/
/* P_INT_Ctrl register */
/* bit set */
#define CB_2HZ_INT_EN				0x0001
#define CB_4HZ_INT_EN				0x0001
#define CB_TMB1_INT_EN				0x0001
#define CB_TMB2_INT_EN				0x0001
#define CB_KEY_INT_EN				0x0001
#define CB_EXT1_RISE_TRIGGER		0x0001
#define CB_EXT2_RISE_TRIGGER		0x0001
#define CB_EXT1_INT_EN				0x0001
#define CB_EXT2_INT_EN				0x0001
#define CB_EXT1PIN_INEN				0x0001
#define CB_EXT2PIN_INEN				0x0001
/* word set */
#define CW_2HZ_INT_EN				0x0001 
#define CW_4HZ_INT_EN				(0x0001 << 1)
#define CW_TMB1_INT_EN				(0x0001 << 2)
#define CW_TMB2_INT_EN				(0x0001 << 3)
#define CW_KEY_INT_EN				(0x0001 << 4)
#define CW_EXT1_RISE_TRIGGER		(0x0001 << 5)
#define CW_EXT2_RISE_TRIGGER		(0x0001 << 6)
#define CW_EXT1_INT_EN				(0x0001 << 7)
#define CW_EXT2_INT_EN				(0x0001 << 8)
#define CW_EXT1PIN_INEN				(0x0001 << 9)
#define CW_EXT2PIN_INEN				(0x0001 << 10)


/* P_INT_Priority register */
/* bit set */
#define CB_KEYIP_SET_FIQ			0x0001
#define CB_LVDIP_SET_FIQ			0x0001
#define CB_TMR0IP_SET_FIQ			0x0001
#define CB_TMR1IP_SET_FIQ			0x0001
#define CB_TMR2IP_SET_FIQ			0x0001
#define CB_PCIIP_SET_FIQ			0x0001
#define CB_SIOIP_SET_FIQ			0x0001
#define CB_SPIIP_SET_FIQ			0x0001
#define CB_UARTIP_SET_FIQ			0x0001
#define CB_EXT1IP_SET_FIQ			0x0001
#define CB_EXT2IP_SET_FIQ			0x0001
#define CB_ADCIP_SET_FIQ			0x0001
/* word set */
#define CW_KEYIP_SET_FIQ			(0x0001 << 4)
#define CW_LVDIP_SET_FIQ			(0x0001 << 5)
#define CW_TMR0IP_SET_FIQ			(0x0001 << 6)
#define CW_TMR1IP_SET_FIQ			(0x0001 << 7)
#define CW_TMR2IP_SET_FIQ			(0x0001 << 8)
#define CW_PCIIP_SET_FIQ			(0x0001 << 9)
#define CW_SIOIP_SET_FIQ			(0x0001 << 10)
#define CW_SPIIP_SET_FIQ			(0x0001 << 11)
#define CW_UARTIP_SET_FIQ			(0x0001 << 12)
#define CW_EXT1IP_SET_FIQ			(0x0001 << 13)
#define CW_EXT2IP_SET_FIQ			(0x0001 << 14)
#define CW_ADCIP_SET_FIQ			(0x0001 << 15)


/* P_INT_Status register */
/* bit set */
#define CB_CLEAR_2HZINTF			0x0001
#define CB_CLEAR_4HZINTF			0x0001
#define CB_CLEAR_TMB1INTF			0x0001
#define CB_CLEAR_TMB2INTF			0x0001
#define CB_CLEAR_KEYINTF			0x0001
#define CB_CLEAR_LVDINTF			0x0001
#define CB_CLEAR_TMR0INTF			0x0001
#define CB_CLEAR_TMR1INTF			0x0001
#define CB_CLEAR_TMR2INTF			0x0001
#define CB_CLEAR_PCIINTF			0x0001
#define CB_CLEAR_SIOINTF			0x0001
#define CB_CLEAR_SPIINTF			0x0001
#define CB_CLEAR_UARTINTF			0x0001
#define CB_CLEAR_EXT1INTF			0x0001
#define CB_CLEAR_EXT2INTF			0x0001
#define CB_CLEAR_ADCINTF			0x0001
/* word set */
#define CW_CLEAR_2HZINTF			0x0001
#define CW_CLEAR_4HZINTF			(0x0001 << 1)
#define CW_CLEAR_TMB1INTF			(0x0001 << 2)
#define CW_CLEAR_TMB2INTF			(0x0001 << 3)
#define CW_CLEAR_KEYINTF			(0x0001 << 4)
#define CW_CLEAR_LVDINTF			(0x0001 << 5)
#define CW_CLEAR_TMR0INTF			(0x0001 << 6)
#define CW_CLEAR_TMR1INTF			(0x0001 << 7)
#define CW_CLEAR_TMR2INTF			(0x0001 << 8)
#define CW_CLEAR_PCIINTF			(0x0001 << 9)
#define CW_CLEAR_SIOINTF			(0x0001 << 10)
#define CW_CLEAR_SPIINTF			(0x0001 << 11)
#define CW_CLEAR_UARTINTF			(0x0001 << 12)
#define CW_CLEAR_EXT1INTF			(0x0001 << 13)
#define CW_CLEAR_EXT2INTF			(0x0001 << 14)
#define CW_CLEAR_ADCINTF			(0x0001 << 15)


/* P_TimeBase_Setup register */
/* bit set */		
#define CB_TMBENB_DISABLE		0x0001	
#define CB_TMB1FS_8HZ			0x0000		
#define CB_TMB1FS_16HZ			0x0001		
#define CB_TMB1FS_32HZ			0x0002		
#define CB_TMB1FS_64HZ			0x0003		
#define CB_TMB2FS_128HZ			0x0000
#define CB_TMB2FS_256HZ			0x0001		
#define CB_TMB2FS_512HZ			0x0002	
#define CB_TMB2FS_1024HZ		0x0003	
/* word set */
#define	CW_TMBDefault			0x0000			//TMB default value
#define CW_TMBENB_ENABLE		0x0000			//Ensable TimeBase
#define CW_TMBENB_DISABLE		(0x0001 << 4)	//Disable TimeBase
#define CW_TMB1FS_8HZ			0x0000			//Set TimeBase1 as 8  HZ
#define CW_TMB1FS_16HZ			0x0001			//Set TimeBase1 as 16 HZ
#define CW_TMB1FS_32HZ			0x0002			//Set TimeBase1 as 32 HZ
#define CW_TMB1FS_64HZ			0x0003			//Set TimeBase1 as 64 HZ
#define CW_TMB2FS_128HZ			0x0000			//Set TimeBase2 as 128 HZ
#define CW_TMB2FS_256HZ			(0x0001 << 2)	//Set TimeBase2 as 256 HZ
#define CW_TMB2FS_512HZ			(0x0002 << 2)	//Set TimeBase2 as 512 HZ
#define CW_TMB2FS_1024HZ		(0x0003 << 2)	//Set TimeBase2 as 1024 HZ


/* P_TimeBase_Clr register */
/* word set */
#define 	CW_TMBCLR				0x5555			//Clear TimeBase


/*=================================*/
/* D. I/O Port register			   */
/*=================================*/
/* P_IOn_Dir register */					//n: is A,B,C,D
/* bit set */		
#define CB_PORTPAD0_AS_OUTPUT		0x0001
#define CB_PORTPAD1_AS_OUTPUT		0x0001
#define CB_PORTPAD2_AS_OUTPUT		0x0001
#define CB_PORTPAD3_AS_OUTPUT		0x0001
#define CB_PORTPAD4_AS_OUTPUT		0x0001
#define CB_PORTPAD5_AS_OUTPUT		0x0001
#define CB_PORTPAD6_AS_OUTPUT		0x0001
#define CB_PORTPAD7_AS_OUTPUT		0x0001
#define CB_PORTPAD8_AS_OUTPUT		0x0001
#define CB_PORTPAD9_AS_OUTPUT		0x0001
#define CB_PORTPAD10_AS_OUTPUT		0x0001
#define CB_PORTPAD11_AS_OUTPUT		0x0001
#define CB_PORTPAD12_AS_OUTPUT		0x0001
#define CB_PORTPAD13_AS_OUTPUT		0x0001
#define CB_PORTPAD14_AS_OUTPUT		0x0001
#define CB_PORTPAD15_AS_OUTPUT		0x0001
/* word set */
#define CW_PORTPAD0_AS_OUTPUT		0x0001
#define CW_PORTPAD1_AS_OUTPUT		(0x0001 << 1)
#define CW_PORTPAD2_AS_OUTPUT		(0x0001 << 2)
#define CW_PORTPAD3_AS_OUTPUT		(0x0001 << 3)
#define CW_PORTPAD4_AS_OUTPUT		(0x0001 << 4)
#define CW_PORTPAD5_AS_OUTPUT		(0x0001 << 5)
#define CW_PORTPAD6_AS_OUTPUT		(0x0001 << 6)
#define CW_PORTPAD7_AS_OUTPUT		(0x0001 << 7)
#define CW_PORTPAD8_AS_OUTPUT		(0x0001 << 8)
#define CW_PORTPAD9_AS_OUTPUT		(0x0001 << 9)
#define CW_PORTPAD10_AS_OUTPUT		(0x0001 << 10)
#define CW_PORTPAD11_AS_OUTPUT		(0x0001 << 11)
#define CW_PORTPAD12_AS_OUTPUT		(0x0001 << 12)
#define CW_PORTPAD13_AS_OUTPUT		(0x0001 << 13)
#define CW_PORTPAD14_AS_OUTPUT		(0x0001 << 14)
#define CW_PORTPAD15_AS_OUTPUT		(0x0001 << 15)


/* P_IOn_Attrib register */					//n: is A,B,C,D
/* bit set */
#define CB_PORTPAD0_NONINV			0x0001	
#define CB_PORTPAD1_NONINV			0x0001	
#define CB_PORTPAD2_NONINV			0x0001	
#define CB_PORTPAD3_NONINV			0x0001	
#define CB_PORTPAD4_NONINV			0x0001
#define CB_PORTPAD5_NONINV			0x0001	
#define CB_PORTPAD6_NONINV			0x0001
#define CB_PORTPAD7_NONINV			0x0001
#define CB_PORTPAD8_NONINV			0x0001	
#define CB_PORTPAD9_NONINV			0x0001
#define CB_PORTPAD10_NONINV			0x0001
#define CB_PORTPAD11_NONINV			0x0001
#define CB_PORTPAD12_NONINV			0x0001
#define CB_PORTPAD13_NONINV			0x0001
#define CB_PORTPAD14_NONINV			0x0001
#define CB_PORTPAD15_NONINV			0x0001
/* word set */
#define CW_PORTPAD0_NONINV			0x0001	
#define CW_PORTPAD1_NONINV			(0x0001 << 1)	
#define CW_PORTPAD2_NONINV			(0x0001 << 2)	
#define CW_PORTPAD3_NONINV			(0x0001 << 3)	
#define CW_PORTPAD4_NONINV			(0x0001 << 4)	
#define CW_PORTPAD5_NONINV			(0x0001 << 5)	
#define CW_PORTPAD6_NONINV			(0x0001 << 6)	
#define CW_PORTPAD7_NONINV			(0x0001 << 7)	
#define CW_PORTPAD8_NONINV			(0x0001 << 8)	
#define CW_PORTPAD9_NONINV			(0x0001 << 9)	
#define CW_PORTPAD10_NONINV			(0x0001 << 10)
#define CW_PORTPAD11_NONINV			(0x0001 << 11)
#define CW_PORTPAD12_NONINV			(0x0001 << 12)
#define CW_PORTPAD13_NONINV			(0x0001 << 13)
#define CW_PORTPAD14_NONINV			(0x0001 << 14)
#define CW_PORTPAD15_NONINV			(0x0001 << 15)

/* P_IOn_Data/P_IOn_Buffer register */		//n: is A,B,C,D
/* bit set */
#define CB_PORTPAD0_SET_HI			0x0001
#define CB_PORTPAD1_SET_HI			0x0001
#define CB_PORTPAD2_SET_HI			0x0001
#define CB_PORTPAD3_SET_HI			0x0001
#define CB_PORTPAD4_SET_HI			0x0001
#define CB_PORTPAD5_SET_HI			0x0001
#define CB_PORTPAD6_SET_HI			0x0001
#define CB_PORTPAD7_SET_HI			0x0001
#define CB_PORTPAD8_SET_HI			0x0001
#define CB_PORTPAD9_SET_HI			0x0001
#define CB_PORTPAD10_SET_HI			0x0001
#define CB_PORTPAD11_SET_HI			0x0001
#define CB_PORTPAD12_SET_HI			0x0001
#define CB_PORTPAD13_SET_HI			0x0001
#define CB_PORTPAD14_SET_HI			0x0001
#define CB_PORTPAD15_SET_HI			0x0001
/* word set */
#define CW_PORTPAD0_SET_HI			0x0001
#define CW_PORTPAD1_SET_HI			(0x0001 << 1)
#define CW_PORTPAD2_SET_HI			(0x0001 << 2)
#define CW_PORTPAD3_SET_HI			(0x0001 << 3)
#define CW_PORTPAD4_SET_HI			(0x0001 << 4)
#define CW_PORTPAD5_SET_HI			(0x0001 << 5)
#define CW_PORTPAD6_SET_HI			(0x0001 << 6)
#define CW_PORTPAD7_SET_HI			(0x0001 << 7)
#define CW_PORTPAD8_SET_HI			(0x0001 << 8)
#define CW_PORTPAD9_SET_HI			(0x0001 << 9)
#define CW_PORTPAD10_SET_HI			(0x0001 << 10)
#define CW_PORTPAD11_SET_HI			(0x0001 << 11)
#define CW_PORTPAD12_SET_HI			(0x0001 << 12)
#define CW_PORTPAD13_SET_HI			(0x0001 << 13)
#define CW_PORTPAD14_SET_HI			(0x0001 << 14)
#define CW_PORTPAD15_SET_HI			(0x0001 << 15)


/*=================================*/
/* E. LVD and LVR register		   */	
/*=================================*/
/* P_LVDLVR_Ctrl register*/
/* bit set */
#define CB_LVDLS_2_6V					0x0000
#define CB_LVDLS_2_8V					0x0001
#define CB_LVDLS_3_0V					0x0002
#define CB_LVDLS_3_2V					0x0003
#define CB_LVD_INT_EN					0x0001
#define CB_LVD_SOFT_CTRL_DISABLE		0x0001
#define CB_LVD_REFVOL_EN				0x0001
#define CB_LVDPWR_SOFT_CTRL_DISABLE 	0x0001
/* word set */
#define CW_LVDLS_2_6V					0x0000
#define CW_LVDLS_2_8V					0x0001
#define CW_LVDLS_3_0V					0x0002
#define CW_LVDLS_3_2V					0x0003
#define CW_LVD_INT_EN					(0x0001 << 2)
#define CW_LVD_SOFT_CTRL_DISABLE		(0x0001 << 3)
#define CW_LVD_REFVOL_EN				(0x0001 << 4)
#define CW_LVDPWR_SOFT_CTRL_DISABLE 	(0x0001 << 5)


/* P_LVD_Status register*/
/* bit set */
#define	CB_LVDIF						0x0001
/* word set */
#define	CW_LVDIF						0x0001			//LVD Interrupt Flag


/*=================================*/
/* F. Power saving mode and wakup  */
/