📄 spmc70_regs.h
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UInt16 UARTTIF : 1;
UInt16 UARTTPE : 1;
UInt16 UARTTFE : 1;
UInt16 UARTROR : 1;
UInt16 UARTBMPT : 1;
UInt16 UARTTBY : 1;
UInt16 UARTRBF : 1;
UInt16 reserved : 8;
} B;
} P_UART_Status_DEF;
/*****************************************************************************/
/* L. 10-bit ADC converter register */
/*****************************************************************************/
/*****************************************************************************/
/* ADC control register (P_ADC_Ctrl) */
/* bit 0 : ADCEN, A/D converter enable */
/* bit 1 : ADCCSB, A/D converter chip select */
/* = 0, select ADC block */
/* = 1, un-select ADC block */
/* bit 3 - 2 : ADCFS, A/D converter clock selection */
/* = 00, CPUCLK / 16 */
/* = 01, CPUCLK / 32 */
/* = 10, CPUCLK / 64 */
/* = 11, CPUCLK / 128 */
/* bit 6 - 4 : ADCCHS, select A/D converter channel input */
/* = 000, AD0 */
/* = 001, AD1 */
/* = 010, AD2 */
/* = 011, AD3 */
/* = 100, AD4 */
/* = 101, AD5 */
/* = 110, AD6 */
/* = 111, AD7 */
/* bit 7 : reserved */
/* bit 8 : ADCTREF, ADC VDD reference voltage select */
/* = 1, ADC top reference volatge equal to VRT pin */
/* = 0, ADC top reference volatge equal to AVDD pin */
/* bit 9 : ADCIEN, ADC conversion ready status interrupt enable */
/* bit 10 : ADC8KTRG, ADC conversion request with constant frquency 8KHz */
/* 1 = enable */
/* bit 11 : ADCEXTRG, external ADC conversion request trigger from PB8 */
/* 1 = enable */
/* bit 12 : ADCTRG, software ADC conversion request */
/* 1 = enable */
/* bit 13 : ADCIF, ADC conversion ready status */
/* 1 = conversion ready */
/* bit 14-15 : reserved */
/*****************************************************************************/
typedef union
{
UInt16 W;
struct
{
UInt16 ADCEN : 1;
UInt16 ADCCSB : 1;
UInt16 ADCFS : 2;
UInt16 ADCCHS : 3;
UInt16 reserved1 : 1;
UInt16 ADCTREF : 1;
UInt16 ADCIEN : 1;
UInt16 ADC8KTRG : 1;
UInt16 ADCEXTRG : 1;
UInt16 ADCTRG : 1;
UInt16 ADCIF : 1;
UInt16 reserved2 : 2;
} B;
} P_ADC_Ctrl_DEF;
/*****************************************************************************/
/* ADC data and status register (P_ADC_Data) */
/* bit 9 - 0 : ADCData, ADC conversion data */
/* bit 10 - 14: reserved */
/* bit 15 : ADCRDY, ADC conversion ready */
/* = 1, conversion ready */
/*****************************************************************************/
typedef union
{
UInt16 W;
struct
{
UInt16 ADCData : 10;
UInt16 reserved : 1;
UInt16 ADCRDY : 1;
} B;
} P_ADC_Data_DEF;
/*****************************************************************************/
/* System Option Register (P_System_Option) */
/* bit 0 : CLK Source, Clock Source Selection */
/* bit 1 : WDG, enable watchdog function */
/* bit 2 : LVR, enable low voltage reset function */
/* bit 3 : LVD, enable low voltage detection function */
/* bit 4 : Security, security selection bit */
/* bit 5 - 15 : Verification Pattern, Writer will write 010 1010 1010(0x2AA) to this area */
/*****************************************************************************/
typedef union
{
UInt16 W;
struct
{
UInt16 CLK : 1;
UInt16 WDG : 1;
UInt16 LVR : 1;
UInt16 LVD : 1;
UInt16 Security : 1;
UInt16 Verification : 11;
} B;
} P_System_Option_DEF;
/*****************************************************************************/
/* SPMC70 family register structure macro definition */
/*****************************************************************************/
/* A. CPU control registers */
#define P_Clk_Ctrl ((volatile P_Clk_Ctrl_DEF *)(P_Clk_Ctrl_ADDR))
#define P_WatchDog_Ctrl ((volatile P_WatchDog_Ctrl_DEF *)(P_WatchDog_Ctrl_ADDR))
#define P_WatchDog_Clr ((volatile GEN_REG_DEF *)(P_WatchDog_Clr_ADDR))
#define P_Reset_Status ((volatile P_Reset_Status_DEF *)(P_Reset_Status_ADDR))
#define P_System_Option ((volatile P_System_Option_DEF *)(P_System_Option_ADDR))
/* B. Flash organization and control register */
#define P_Flash_RW ((volatile GEN_REG_DEF *)(P_Flash_RW_ADDR))
#define P_Flash_Ctrl ((volatile GEN_REG_DEF *)(P_Flash_Ctrl_ADDR))
#define P_Wait_State ((volatile GEN_REG_DEF *)(P_Wait_State_ADDR))
/* C. Interrupt control register */
#define P_INT_Ctrl ((volatile P_INT_Ctrl_DEF *)(P_INT_Ctrl_ADDR))
#define P_INT_Priority ((volatile P_INT_Priority_DEF *)(P_INT_Priority_ADDR))
#define P_INT_Status ((volatile P_INT_Status_DEF *)(P_INT_Status_ADDR))
#define P_TimeBase_Setup ((volatile P_TimeBase_Setup_DEF *)(P_TimeBase_Setup_ADDR))
#define P_TimeBase_Clr ((volatile GEN_REG_DEF *)(P_TimeBase_Clr_ADDR))
/* D. I/O Ports */
#define P_IOA_Data ((volatile GEN_REG_DEF *)(P_IOA_Data_ADDR))
#define P_IOA_Buffer ((volatile GEN_REG_DEF *)(P_IOA_Buffer_ADDR))
#define P_IOA_Dir ((volatile GEN_REG_DEF *)(P_IOA_Dir_ADDR))
#define P_IOA_Attrib ((volatile GEN_REG_DEF *)(P_IOA_Attrib_ADDR))
#define P_IOA_Latch ((volatile GEN_REG_DEF *)(P_IOA_Latch_ADDR))
#define P_IOB_Data ((volatile GEN_REG_DEF *)(P_IOB_Data_ADDR))
#define P_IOB_Buffer ((volatile GEN_REG_DEF *)(P_IOB_Buffer_ADDR))
#define P_IOB_Dir ((volatile GEN_REG_DEF *)(P_IOB_Dir_ADDR))
#define P_IOB_Attrib ((volatile GEN_REG_DEF *)(P_IOB_Attrib_ADDR))
#define P_IOB_Latch ((volatile GEN_REG_DEF *)(P_IOB_Latch_ADDR))
#define P_IOC_Data ((volatile GEN_REG_DEF *)(P_IOC_Data_ADDR))
#define P_IOC_Buffer ((volatile GEN_REG_DEF *)(P_IOC_Buffer_ADDR))
#define P_IOC_Dir ((volatile GEN_REG_DEF *)(P_IOC_Dir_ADDR))
#define P_IOC_Attrib ((volatile GEN_REG_DEF *)(P_IOC_Attrib_ADDR))
#define P_IOC_Latch ((volatile GEN_REG_DEF *)(P_IOC_Latch_ADDR))
#define P_IOD_Data ((volatile GEN_REG_DEF *)(P_IOD_Data_ADDR))
#define P_IOD_Buffer ((volatile GEN_REG_DEF *)(P_IOD_Buffer_ADDR))
#define P_IOD_Dir ((volatile GEN_REG_DEF *)(P_IOD_Dir_ADDR))
#define P_IOD_Attrib ((volatile GEN_REG_DEF *)(P_IOD_Attrib_ADDR))
#define P_IOD_Latch ((volatile GEN_REG_DEF *)(P_IOD_Latch_ADDR))
/* E. LVR and LVD register */
#define P_LVDLVR_Ctrl ((volatile P_LVDLVR_Ctrl_DEF *)(P_LVDLVR_Ctrl_ADDR))
#define P_LVD_Status ((volatile P_LVD_Status_DEF *)(P_LVD_Status_ADDR))
/* F. Power saving modes and wakeup register */
#define P_Wakeup_Source ((volatile P_Wakeup_Source_DEF *)(P_Wakeup_Source_ADDR))
#define P_Halt_Enter ((volatile GEN_REG_DEF *)(P_Halt_Enter_ADDR))
#define P_Stdby_Enter ((volatile GEN_REG_DEF *)(P_Stdby_Enter_ADDR))
#define P_Wakeup_Status ((volatile P_Wakeup_Status_DEF *)(P_Wakeup_Status_ADDR))
#define P_Sleep_Enter ((volatile GEN_REG_DEF *)(P_Sleep_Enter_ADDR))
/* G. Parallel Communication Interface PCI register */
#define P_PCI_Ctrl ((volatile P_PCI_Ctrl_DEF *)(P_PCI_Ctrl_ADDR))
#define P_PCI_Status ((volatile P_PCI_Status_DEF *)(P_PCI_Status_ADDR))
#define P_PCI_RxBuf ((volatile P_PCI_RxBUF_DEF *)(P_PCI_RxBuf_ADDR))
#define P_PCI_TxBuf ((volatile P_PCI_TxBUF_DEF *)(P_PCI_TxBuf_ADDR))
#define P_PCI_COMM ((volatile GEN_REG_DEF *)(P_PCI_COMM_ADDR))
/* H. Timer0/Timer1/Timer2 register */
#define P_Timer0_Ctrl ((volatile P_Timer0_Ctrl_DEF *)(P_Timer0_Ctrl_ADDR))
#define P_Timer0_Preload ((volatile GEN_REG_DEF *)(P_Timer0_Preload_ADDR))
#define P_Timer0_CCPR ((volatile GEN_REG_DEF *)(P_Timer0_CCPR_ADDR))
#define P_Timer0_CCPR2 ((volatile GEN_REG_DEF *)(P_Timer0_CCPR2_ADDR))
#define P_Timer1_Ctrl ((volatile P_Timer1_Ctrl_DEF *)(P_Timer1_Ctrl_ADDR))
#define P_Timer1_Preload ((volatile GEN_REG_DEF *)(P_Timer1_Preload_ADDR))
#define P_Timer1_CCPR ((volatile GEN_REG_DEF *)(P_Timer1_CCPR_ADDR))
#define P_Timer1_CCPR2 ((volatile GEN_REG_DEF *)(P_Timer1_CCPR2_ADDR))
#define P_Timer2_Ctrl ((volatile P_Timer2_Ctrl_DEF *)(P_Timer2_Ctrl_ADDR))
#define P_Timer2_Preload ((volatile GEN_REG_DEF *)(P_Timer2_Preload_ADDR))
/* I. SPI register */
#define P_SPI_Ctrl ((volatile P_SPI_Ctrl_DEF *)(P_SPI_Ctrl_ADDR))
#define P_SPI_Status ((volatile P_SPI_Status_DEF *)(P_SPI_Status_ADDR))
#define P_SPI_TxBuf ((volatile GEN_REG_DEF *)(P_SPI_TxBuf_ADDR))
#define P_SPI_RxBuf ((volatile GEN_REG_DEF *)(P_SPI_RxBuf_ADDR))
/* J. SIO register */
#define P_SIO_Ctrl ((volatile P_SIO_Ctrl_DEF *)(P_SIO_Ctrl_ADDR))
#define P_SIO_Status ((volatile P_SIO_Status_DEF *)(P_SIO_Status_ADDR))
#define P_SIO_Buf ((volatile GEN_REG_DEF *)(P_SIO_Buf_ADDR))
#define P_SIO_Addr ((volatile GEN_REG_DEF *)(P_SIO_Addr_ADDR))
/* K. UART register */
#define P_UART_Ctrl ((volatile P_UART_Ctrl_DEF *)(P_UART_Ctrl_ADDR))
#define P_UART_Status ((volatile P_UART_Status_DEF *)(P_UART_Status_ADDR))
#define P_UART_Reset ((volatile GEN_REG_DEF *)(P_UART_Reset_ADDR))
#define P_UART_BaudRateL ((volatile GEN_REG_DEF *)(P_UART_BaudRateL_ADDR))
#define P_UART_BaudRateH ((volatile GEN_REG_DEF *)(P_UART_BaudRateH_ADDR))
#define P_UART_TxBuf ((volatile GEN_REG_DEF *)(P_UART_TxBuf_ADDR))
#define P_UART_RxBuf ((volatile GEN_REG_DEF *)(P_UART_RxBuf_ADDR))
/* L. ADC register */
#define P_ADC_Ctrl ((volatile P_ADC_Ctrl_DEF *)(P_ADC_Ctrl_ADDR))
#define P_ADC_Data ((volatile P_ADC_Data_DEF *)(P_ADC_Data_ADDR))
/*****************************************************************************/
/* Chip-intrnal register constant macro definition */
/*****************************************************************************/
#define BIT0 0
#define BIT1 1
#define BIT2 2
#define BIT3 3
#define BIT4 4
#define BIT5 5
#define BIT6 6
#define BIT7 7
#define BIT8 8
#define BIT9 9
#define BIT10 10
#define BIT11 11
#define BIT12 12
#define BIT13 13
#define BIT14 14
#define BIT15 15
/*=================================*/
/* A. flash control register */
/*=================================*/
/* P_System_Option register */
/* bit set */
#define CB_SYS_CLK_R 0x0000 //R oscillator
#define CB_SYS_CLK_OSC 0x0001 //crystal oscillator
#define CB_SYS_WDG_Disable 0x0000 //disable watchdog function
#define CB_SYS_WDG_Enable 0x0001 //enable watchdog function
#define CB_SYS_LVR_Disable 0x0000 //disable low voltage reset function
#define CB_SYS_LVR_Enable 0x0001 //enable low voltage reset function
#define CB_SYS_LVD_Disable 0x0000 //disable low voltage detection function
#define CB_SYS_LVD_Enable 0x0001 //enable low voltage detection function
#define CB_SYS_Security_Protect 0x0000 //the normal block in the flash cannot be accessed
#define CB_SYS_Security_NoProtect 0x0001 //not protect, can be readable or write-able
#define CB_SYS_Verification 0x02AA //Verification Pattern
/* word set */
#define CW_SYS_CLK_R 0x0000
#define CW_SYS_CLK_OSC 0x0001
#define CW_SYS_WDG_Disable 0x0000
#define CW_SYS_WDG_Enable (0x0001 << 1)
#define CW_SYS_LVR_Disable 0x0000
#define CW_SYS_LVR_Enable (0x0001 << 2)
#define CW_SYS_LVD_Disable 0x0000
#define CW_SYS_LVD_Enable (0x0001 << 3)
#define CW_SYS_Security_Protect 0x0000
#define CW_SYS_Security_NoProtect (0x0001 << 4)
#define CW_SYS_Verification (0x02AA << 5)
/* P_Flash_RW register */
/* bit set */
#define CB_BK14WDIS 0x0001
#define CB_BK13WDIS 0x0001
#define CB_BK12WDIS 0x0001
#define CB_BK11WDIS 0x0001
#define CB_BK10WDIS 0x0001
#define CB_BK9WDIS 0x0001
#define CB_BK8WDIS 0x0001
#define CB_BK7WDIS 0x0001
#define CB_BK6WDIS 0x0001
#define CB_BK5WDIS 0x0001
#define CB_BK4WDIS 0x0001
#define CB_BK3WDIS 0x0001
#define CB_BK2WDIS 0x0001
#define CB_BK1WDIS 0x0001
#define CB_BK0WDIS 0x0001
/* word set */
#define CW_BK14WDIS (0x0001 << 14) //BANK 14 Write Disable
#define CW_BK13WDIS (0x0001 << 13) //BANK 13 Write Disable
#define CW_BK12WDIS (0x0001 << 12) //BANK 12 Write Disable
#define CW_BK11WDIS (0x0001 << 11) //BANK 11 Write Disable
#define CW_BK10WDIS (0x0001 << 10) //BANK 10 Write Disable
#define CW_BK9WDIS (0x0001 << 9) //BANK 9 Write Disable
#define CW_BK8WDIS (0x0001 << 8) //BANK 8 Write Disable
#define CW_BK7WDIS (0x0001 << 7) //BANK 7 Write Disable
#define CW_BK6WDIS (0x0001 << 6) //BANK 6 Write Disable
#define CW_BK5WDIS (0x0001 << 5) //BANK 5 Write Disable
#define CW_BK4WDIS (0x0001 << 4) //BANK 4 Write Disable
#define CW_BK3WDIS (0x0001 << 3) //BANK 3 Write Disable
#define CW_BK2WDIS (0x0001 << 2) //BANK 2 Write Disable
#define CW_BK1WDIS (0x0001 << 1) //BANK 1 Write Disable
#define CW_BK0WDIS 0x0001 //BANK 0 Write Disable
/* P_Flash_Ctrl register */
/* word set */
#define CW_FlashRW_CMD 0x5A5A //Flash RW Command
#define CW_FlashCMD 0xAAAA //Flash Command FLash Block
#define CW_PageErase 0x5511 //Flash Page Erase Command
#define CW_Program 0x5533 //Flash Program Command
#define CW_Sequential 0x5544 //Flash Sequential Program Command
#define CW_SequentialEnd 0xFFFF //Flash Sequential Program End Command
/* P_Wait_State register */
/* word set */
#define CW_WSCYCT_1 0x0001 //Wait Cycle 1
#define CW_WSCYCT_2 0x0002 //Wait Cycle 2
#define CW_WSCYCT_3 0x0003 //Wait Cycle 3
#define CW_WSCYCT_4 0x0004 //Wait Cycle 4
#define CW_WSCYCT_5 0x0005 //Wait Cycle 5
#define CW_WSCYCT_6 0x0006 //Wait Cycle 6
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