📄 spmc70_regs.h
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/* = 1111, PWM mode, return to zero output (RTZ) */
/* bit 12 - 11: EXT2PS, counter mode prescalr selection for EXT2 */
/* = 00, every falling edge */
/* = 01, every rising edge */
/* = 10, every 4 rising edge */
/* = 11, every 16 rising edge */
/* bit 13 : TMR0IEN, timer 0 interrupt enable */
/* bit 14 : TMR0IF, timer 0 interrupt flag, must be clear by software */
/* bit 15 : TMR0EN, timer 0 enable */
/* = 1, enable timer 0 counter or CCP mode */
/*****************************************************************************/
typedef union
{
UInt16 W;
struct
{
UInt16 CLKAFS : 3;
UInt16 CLKBFS : 3;
UInt16 SYNCLK : 1;
UInt16 CCP0MS : 4;
UInt16 EXT2PS : 2;
UInt16 TMR0IEN : 1;
UInt16 TMR0IF : 1;
UInt16 TMR0EN : 1;
} B;
} P_Timer0_Ctrl_DEF;
/*****************************************************************************/
/* Timer 1 control/status register (P_Timer1_Ctrl) */
/* bit 2 - 0 : CLKAFS, clock source A frequency selection */
/* = 000, CPUCLK / 2 */
/* = 001, CPUCLK / 256 */
/* = 010, 32768 Hz */
/* = 011, 8192 Hz */
/* = 100, 4096 Hz */
/* = 101, 1 */
/* = 110, 0 */
/* = 111, EXT1 */
/* bit 5 - 3 : reserved */
/* bit 6 : SYNCLK, the clock source of TMR0 is synchronized by CPUCLK */
/* = 1, synchronized */
/* = 0, non synchronized */
/* bit 10 - 7 : CCP1MS, Timer 1 CCP1 mode selection */
/* = 0000, capture/compare/PWM are off */
/* = 0100, capture mode, every falling edge */
/* = 0101, capture mode, every rising edge */
/* = 0110, capture mode, every 4 rising edge */
/* = 0111, capture mode, every 16 rising edge */
/* = 1000, compare mode, set output (CCP0IF set) */
/* = 1001, compare mode, clear output (CCP0IF set) */
/* = 101x, compare mode, CCP1 unaffected (CCP1IF set) */
/* = 1100, PWM mode, not return to one output (NRO) */
/* = 1101, PWM mode, not return to zero output (NRZ) */
/* = 1110, PWM mode, return to one output (RTO) */
/* = 1111, PWM mode, return to zero output (RTZ) */
/* bit 12 - 11: EXT1PS, counter mode prescalr selection for EXT1 */
/* = 00, every falling edge */
/* = 01, every rising edge */
/* = 10, every 4 rising edge */
/* = 11, every 16 rising edge */
/* bit 13 : TMR1IEN, timer 1 interrupt enable */
/* bit 14 : TMR1IF, timer 1 interrupt flag, must be clear by software */
/* bit 15 : TMR1EN, timer 1 enable */
/* = 1, enable timer 1 counter or CCP mode */
/*****************************************************************************/
typedef union
{
UInt16 W;
struct
{
UInt16 CLKAFS : 3;
UInt16 reserved : 3;
UInt16 SYNCLK : 1;
UInt16 CCP1MS : 4;
UInt16 EXT1PS : 2;
UInt16 TMR1IEN : 1;
UInt16 TMR1IF : 1;
UInt16 TMR1EN : 1;
} B;
} P_Timer1_Ctrl_DEF;
/*****************************************************************************/
/* Timer 2 control/status register (P_Timer2_Ctrl) */
/* bit 2 - 0 : CLKAFS, clock source A frequency selection */
/* = 000, CPUCLK / 2 */
/* = 001, CPUCLK / 256 */
/* = 010, 32768 Hz */
/* = 011, 8192 Hz */
/* = 100, 4096 Hz */
/* = 101, 1 */
/* = 110, 0 */
/* = 111, EXT1 */
/* bit 5 - 3 : reserved */
/* bit 6 : SYNCLK, the clock source of TMR2 is synchronized by CPUCLK */
/* = 1, synchronized */
/* = 0, non synchronized */
/* bit 10 - 7 : reserved */
/* bit 12 - 11: EXT1PS, counter mode prescalr selection for EXT1 */
/* = 00, every falling edge */
/* = 01, every rising edge */
/* = 10, every 4 rising edge */
/* = 11, every 16 rising edge */
/* bit 13 : TMR2IEN, timer 2 interrupt enable */
/* bit 14 : TMR2IF, timer 2 interrupt flag, must be clear by software */
/* bit 15 : TMR2EN, timer 2 enable */
/*****************************************************************************/
typedef union
{
UInt16 W;
struct
{
UInt16 CLKAFS : 3;
UInt16 reserved1 : 3;
UInt16 SYNCLK : 1;
UInt16 reserved2 : 4;
UInt16 EXT1PS : 2;
UInt16 TMR2IEN : 1;
UInt16 TMR2IF : 1;
UInt16 TMR2EN : 1;
} B;
} P_Timer2_Ctrl_DEF;
/*****************************************************************************/
/* I. Standard Peripheral Interface SPI register */
/*****************************************************************************/
/*****************************************************************************/
/* SPI control register (P_SPI_Ctrl) */
/* bit 2 - 0 : SPIFS, master mode clock frequency selection */
/* = 000, CPUCLK / 4 */
/* = 001, CPUCLK / 8 */
/* = 010, CPUCLK / 16 */
/* = 011, CPUCLK / 32 */
/* = 100, CPUCLK / 64 */
/* = 101, CPUCLK / 128 */
/* = 11x, reserved */
/* bit 3 : SPIPOL, SPI clock polarity */
/* bit 4 : SPIPHA, SPI clock phase */
/* bit 5 : SPISMPS, SPI sampling mode selection */
/* = 1, input data sampled at end of data ouput time */
/* = 0, input data sampled at middle of data ouput time */
/* bit 6 : SPIMS, SPI mode selection */
/* = 0, master mode */
/* = 1, slave mode */
/* bit 7 : SPIIEN, SPI interrupt enable */
/* bit 8 : SPIEN, SPI enable */
/* bit 9 : SPICSEN, SS\ control enable for slave mode */
/* = 1, IOA15 is shared with SIO clock pin and SS\ pin */
/* = 0, disable */
/* bit 10 - 15: reserved */
/*****************************************************************************/
typedef union
{
UInt16 W;
struct
{
UInt16 SPIFS : 3;
UInt16 SPIPOL : 1;
UInt16 SPIPHA : 1;
UInt16 SPISMPS : 1;
UInt16 SPIMS : 1;
UInt16 SPIIEN : 1;
UInt16 SPIEN : 1;
UInt16 SPICSEN : 1;
UInt16 reserved : 6;
} B;
} P_SPI_Ctrl_DEF;
/*****************************************************************************/
/* SPI status register (P_SPI_Status) */
/* bit 0 : SPIIF, SPI interrupt flag */
/* = 1, when 8 bit TX data has been shitfed out through SDO or */
/* the the 8 bit data has been loaded into SPIBUF */
/* bit 1 : SPITBF, transmission buffer full flag */
/* = 1, transmission buffer full */
/* bit 2 : SPIROR, receving overrun error indication */
/* = 1, overrun error occurs */
/* bit 3 - 15 : reserved */
/*****************************************************************************/
typedef union
{
UInt16 W;
struct
{
UInt16 SPIIF : 1;
UInt16 SPITBF : 1;
UInt16 SPIROR : 1;
UInt16 reserved : 13;
} B;
} P_SPI_Status_DEF;
/*****************************************************************************/
/* J. Serial input and output SIO register */
/*****************************************************************************/
/*****************************************************************************/
/* SIO control register (P_SIO_Ctrl) */
/* bit 1 - 0 : SIOMS, SIO operation mode selection */
/* = 00, slave mode */
/* = 01, salve mode with start and stop bit interrupt enabled */
/* = 1x, software controlled master mode, slave idle */
/* bit 2 : SIOADRMS, address mode selection */
/* = 1, 10 bit address mode */
/* = 0, 7 bit address mode */
/* bit 3 : reserved */
/* bit 4 : SIOIEN, SIO interrupt enable */
/* bit 5 : SIOSDAOLB, SIO SDA release control */
/* = 1, release SDA */
/* = 0, hold SDA low */
/* bit 6 : SIOSCKOLB, SIO SCL clock output control */
/* = 1, release SCL */
/* = 0, hold clock low */
/* bit 7 : SIOEN, SIO enable */
/* = 1, enable the serial port and configures the SDA and SCL */
/* as the source of the serial port pins */
/* = 0, disable serial port and configures these pins as I/O */
/* port pins */
/* bit 8 - 15 : reserved */
/*****************************************************************************/
typedef union
{
UInt16 W;
struct
{
UInt16 SIOMS : 2;
UInt16 SIOADRMS : 1;
UInt16 reserved1 : 1;
UInt16 SIOIEN : 1;
UInt16 SIOSDAOLB : 1;
UInt16 SIOSCKOLB : 1;
UInt16 SIOEN : 1;
UInt16 reserved2 : 8;
} B;
} P_SIO_Ctrl_DEF;
/*****************************************************************************/
/* SIO status register (P_SIO_Status) */
/* bit 0 : SIOBF, buffer full status bit */
/* receive mode : */
/* = 1, receive complete, SIOBUF is full */
/* = 0, receive is not complete, SIOBUF is empty or is cleared */
/* by reading in software */
/* transmit mode : */
/* = 1, transmit in progress, SIOBUF is full */
/* = 0, transmit complete, SIOBUF is empty */
/* bit 1 : SIOUA, update address (10-bit address mode only) */
/* = 1, indicate that the user needs to update the address in */
/* SIOADDR register */
/* = 0, address does not need to be updated */
/* bit 2 : SIODIRT, direction selection for read/write information */
/* = 1, read */
/* = 0, write */
/* bit 3 : SIOSTRT, start bit */
/* = 1, a start bit has been detected last */
/* bit 4 : SIOSTOP, stop bit */
/* = 1, a stop bit has been detected last */
/* bit 5 : SIODAT, data type for selection data or address bit */
/* = 1, the last byte received or transmitted was data */
/* = 0, the last byte received or transmitted was address */
/* bit 6 : SIOROR, SIO receive overrrun */
/* bit 7 : SIOIF, SIO interrupt flag, must be cleared by writting '1' */
/* bit 8 : NACK, SIO not-acknowledge status */
/* = 1, non-acknowledge condition occur */
/* bit 9 - 15 : reserved */
/*****************************************************************************/
typedef union
{
UInt16 W;
struct
{
UInt16 SIOBF : 1;
UInt16 SIOUA : 1;
UInt16 SIODIRT : 1;
UInt16 SIOSTRT : 1;
UInt16 SIOSTOP : 1;
UInt16 SIODAT : 1;
UInt16 SIOROR : 1;
UInt16 SIOIF : 1;
UInt16 NACK : 1;
UInt16 reserved : 7;
} B;
} P_SIO_Status_DEF;
/*****************************************************************************/
/* K. Universal Asychronous Receiver/Trasmit UART register */
/*****************************************************************************/
/*****************************************************************************/
/* UART control register (P_UART_Ctrl) */
/* bit 0 : UARTRIEN, uart receiving interrupt enable */
/* bit 1 : UARTTIEN, uart transmission interrupt enable */
/* bit 2 : UARTPMS, parity mode selection */
/* = 1, even parity */
/* = 0, odd parity */
/* bit 3 : UARTPEN, parity check enable */
/* bit 4 : UARTMPEN, multiprocessor communication enable */
/* bit 5 : UARTMS, mode selection */
/* = 1, 11 bit mode, start + 8 bit data + 9th data bit + stop */
/* = 0, 10 bit mode, start + 8 bit data + stop */
/* bit 6 : UARTREN, receving enable */
/* bit 7 : UARTTEN, transmission enable */
/* bit 8 - 15 : reserved */
/*****************************************************************************/
typedef union
{
UInt16 W;
struct
{
UInt16 UARTRIEN : 1;
UInt16 UARTTIEN : 1;
UInt16 UARTTPMS : 1;
UInt16 UARTPEN : 1;
UInt16 UARTMPEN : 1;
UInt16 UARTMS : 1;
UInt16 UARTREN : 1;
UInt16 UARTTEN : 1;
UInt16 reserved : 8;
} B;
} P_UART_Ctrl_DEF;
/*****************************************************************************/
/* UART status register (P_UART_Status) */
/* bit 0 : UARTRIF, UART receving interrupt flag */
/* = 1, a valid byte receiving complete */
/* bit 1 : UARTTIF, UART transmission interrupt flag */
/* = 1, a byte transmission complete */
/* bit 2 : UARTPE, parity error */
/* bit 3 : UARTFE, frame error */
/* bit 4 : UARTROR, receive overrun error */
/* bit 5 : UARTBMPT, the state of bit 9 in 11 bit mode */
/* bit 6 : UARTTBY, transmitter is busy */
/* bit 7 : UARTRBF, receive buffer is full */
/* bit 8 - 15 : reserved */
/*****************************************************************************/
typedef union
{
UInt16 W;
struct
{
UInt16 UARTRIF : 1;
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