📄 spmc70_regs.h
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} P_INT_Priority_DEF;
/*****************************************************************************/
/* Interrupt status register (P_INT_Status) */
/* bit 0 : 2HZINT, 2Hz interrupt flag */
/* bit 1 : 4HZINT, 4Hz interrupt flag */
/* bit 2 : TMB1INT, timer base 1 interrupt flag */
/* bit 3 : TMB2INT, timer base 2 interrupt flag */
/* bit 4 : KEYINT, key change interrupt flag */
/* bit 5 : LVDINT, low voltage detect interrupt flag */
/* bit 6 : TMR0INT, timer 0 interrupt flag */
/* bit 7 : TMR1INT, timer 1 interrupt flag */
/* bit 8 : TMR2INT, timer 2 interrupt flag */
/* bit 9 : PCIINT, PCI interrupt flag */
/* bit 10 : SIOINT, SIO interrupt flag */
/* bit 11 : SPIINT, SPI interrupt flag */
/* bit 12 : UARTINT, UART interrupt flag */
/* bit 13 : EXT1INT, EXT1 interrupt flag */
/* bit 14 : EXT2INT, EXT2 interrupt flag */
/* bit 15 : ADCINT, ADC interrupt flag */
/*****************************************************************************/
typedef union
{
UInt16 W;
struct
{
UInt16 _2HZINT : 1;
UInt16 _4HZINT : 1;
UInt16 TMB1INT : 1;
UInt16 TMB2INT : 1;
UInt16 KEYINT : 1;
UInt16 LVDINT : 1;
UInt16 TMR0INT : 1;
UInt16 TMR1INT : 1;
UInt16 TMR2INT : 1;
UInt16 PCIINT : 1;
UInt16 SIOINT : 1;
UInt16 SPIINT : 1;
UInt16 UARTINT : 1;
UInt16 EXT1INT : 1;
UInt16 EXT2INT : 1;
UInt16 ADCINT : 1;
} B;
} P_INT_Status_DEF;
/*****************************************************************************/
/* Time base selection register (P_TimeBase_Setup) */
/* bit 1 - 0 : TMB1FS, timer base 1 frequency selection */
/* = 00, 8 Hz */
/* = 01, 16 Hz */
/* = 10, 32 Hz */
/* = 11, 64 Hz */
/* bit 3 - 2 : TMB2FS, timer base 2 frequency selection */
/* = 00, 128 Hz */
/* = 01, 256 Hz */
/* = 10, 512 Hz */
/* = 11, 1024 Hz */
/* bit 4 : TMBENB, timer base enable/disable */
/* 1 = disable, 0 = enable */
/* bit 5 - 15 : reserved */
/*****************************************************************************/
typedef union
{
UInt16 W;
struct
{
UInt16 TMB1FS : 2;
UInt16 TMB2FS : 2;
UInt16 TMBENB : 1;
UInt16 reserved : 11;
} B;
} P_TimeBase_Setup_DEF;
/*****************************************************************************/
/* E. Low voltage reset and low voltage detection register */
/*****************************************************************************/
/*****************************************************************************/
/* LVD/LVR control register (P_LVDLVR_Ctrl) */
/* bit 1 - 0 : LVDLS, low voltage detection level secection */
/* = 00, 2.6V */
/* = 01, 2.8V */
/* = 10, 3.0V */
/* = 11, 3.2V */
/* bit 2 : LVDIEN, low voltage detection interrupt enable */
/* bit 3 : LVRENB, software LVR control */
/* = 1, disable */
/* = 0, enable/disable LVR depend on P_System_Option */
/* bit 4 : VREFENB, reference voltage enable, enable to build reference */
/* voltage. */
/* = 0, enable, = 1, disable */
/* bit 5 : LVDENB, software LVD power control */
/* = 1, disable LVD */
/* = 0, enable/disable LVD depend on P_System_Option */
/* bit 6 - 15 : reserved */
/*****************************************************************************/
typedef union
{
UInt16 W;
struct
{
UInt16 LVDLS : 2;
UInt16 LVDIEN : 1;
UInt16 LVRENB : 1;
UInt16 VREFENB : 1;
UInt16 LVDENB : 1;
UInt16 reserved : 10;
} B;
} P_LVDLVR_Ctrl_DEF;
/*****************************************************************************/
/* LVD status register (P_LVD_Status) */
/* bit 0 : LVDIF, low voltage detection flag */
/* = 1, LVD interrupt occurs */
/* bit 1 - 15 : reserved */
/*****************************************************************************/
typedef union
{
UInt16 W;
struct
{
UInt16 LVDIF : 1;
UInt16 reserved : 15;
} B;
} P_LVD_Status_DEF;
/*****************************************************************************/
/* F. Power saving modes and wakeup register */
/*****************************************************************************/
/*****************************************************************************/
/* Wakeup source register (P_Wakeup_Source) */
/* bit 0 : 2HZWEN, 2Hz wakeup enable */
/* bit 1 : 4HZWEN, 4Hz wakeup enable */
/* bit 2 : TMB1WEN, time base 1 wakeup enable */
/* bit 3 : TMB2WEN, time base 2 wakeup enable */
/* bit 4 : LVDWEN, low-voltage detect wakeup enable */
/* bit 5 : TMR0WEN, timer 0 wakeup enable */
/* bit 6 : TMR1WEN, timer 1 wakeup enable */
/* bit 7 : TMR2WEN, timer 2 wakeup enable */
/* bit 8 : PCIIWEN, PCI interrupt wakeup enable */
/* bit 9 : SIOIWEN, SIO interrupt wakeup enable */
/* bit 10 : SPIIWEN, SPI interrupt wakeup enable */
/* bit 11 : UARTIWEN, UART interrupt wakeup enable */
/* bit 12 : KCDWEN, port D key change wakeup enable */
/* bit 13 : KCCWEN, port C key change wakeup enable */
/* bit 14 : KCBWEN, port B key change wakeup enable */
/* bit 15 : KCAWEN, port A key change wakeup enable */
/*****************************************************************************/
typedef union
{
UInt16 W;
struct
{
UInt16 _2HZWEN : 1;
UInt16 _4HZWEN : 1;
UInt16 TMB1WEN : 1;
UInt16 TMB2WEN : 1;
UInt16 LCDWEN : 1;
UInt16 TMR0WEN : 1;
UInt16 TMR1WEN : 1;
UInt16 TMR2WEN : 1;
UInt16 PCIIWEN : 1;
UInt16 SIOIWEN : 1;
UInt16 SPIIWEN : 1;
UInt16 UARTIWEN : 1;
UInt16 KCDWEN : 1;
UInt16 KCCWEN : 1;
UInt16 KCBWEN : 1;
UInt16 KCAWEN : 1;
} B;
} P_Wakeup_Source_DEF;
/*****************************************************************************/
/* Wakeup status register (P_Wakeup_Status) */
/* bit 0 : WAKEUPSF, wakup status flag */
/* = 1, wakeup occurs */
/* bit 1 : STDBYSF, standby mode status flag */
/* = 1, standby mode occurs */
/* bit 2 : reserved */
/* bit 3 : HALTSF, halt mode occurs */
/* bit 4 - 15 : reserved */
/*****************************************************************************/
typedef union
{
UInt16 W;
struct
{
UInt16 WAKEUPSF : 1;
UInt16 STDBYSF : 1;
UInt16 reserved1 : 1;
UInt16 HALTSF : 1;
UInt16 reserved2 : 12;
} B;
} P_Wakeup_Status_DEF;
/*****************************************************************************/
/* G. Parallel Communication Interface register */
/*****************************************************************************/
/*****************************************************************************/
/* PCI control register (P_PCI_Ctrl) */
/* bit 0 - 2 : reserved */
/* bit 3 : RST0EN, system reset output enable, this configuration can */
/* be declared automatically when power on reset occurs */
/* bit 4 : PCIIEN, PCI interrupt enable */
/* bit 5 : PCIMS, PCI mode selection */
/* = 1, master mode */
/* = 0, slave mode */
/* bit 6 : PCIPS, PCI pin mode selection */
/* = 1, 12 pin mode, PCIRDB for read control and */
/* PCIWRB for write control */
/* = 0, 11 pin mode, PCIRDB for read/write control and */
/* PCIWRB for system reset output if RSTEN = 1 */
/* bit 7 : PCIEN, PCI enable */
/* bit 8 - 15 : reserved */
/*****************************************************************************/
typedef union
{
UInt16 W;
struct
{
UInt16 reserved1 : 3;
UInt16 RSTOEN : 1;
UInt16 PCIIEN : 1;
UInt16 PCIMS : 1;
UInt16 PCIPS : 1;
UInt16 PCIEN : 1;
UInt16 reserved : 8;
} B;
} P_PCI_Ctrl_DEF;
/*****************************************************************************/
/* PCI status register (P_PCI_Status) */
/* bit 0 - 1 : reserved */
/* bit 2 : PWRSF, power sleep flag */
/* = 1, in sleep mode */
/* bit 3 : PCIDAT, received data type type */
/* Mater : 1 = from slave's status register */
/* 0 = from slave's output register */
/* Slave : 1 = command */
/* 0 = data */
/* bit 4 : PCIIF, PCI interrupt flag */
/* = 1, when data is received in both modes or transmitted in */
/* slave mode, must be cleared by writting '1' */
/* bit 5 : PCIROR, PCI receive over run error, a new byte received and */
/* and PCIRBF = 1 */
/* = 1, overrun occurs */
/* bit 6 : PCITBF, PCI transmission buffer full, data's being tranmitted*/
/* = 1, output buffer full */
/* = 0, output buffer empty */
/* bit 7 : PCIRBF, PCI receive buffer full, byte receiving complete */
/* = 1, input buffer is full */
/* = 0, input buffer is empty */
/* bit 8 - 15 : reserved */
/*****************************************************************************/
typedef union
{
UInt16 W;
struct
{
UInt16 reserved1 : 2;
UInt16 PWRSF : 1;
UInt16 PCIDAT : 1;
UInt16 PCIIF : 1;
UInt16 PCIROR : 1;
UInt16 PCITBF : 1;
UInt16 PCIRBF : 1;
UInt16 reserved2 : 8;
} B;
} P_PCI_Status_DEF;
/*****************************************************************************/
/* PCI receive/transmiision buffer (P_PCI_RxBuf, P_PCI_TxBuf) */
/* <P_PCI_RxBuf> */
/* bit 7 - 0 : PCIRXBUF, PCI input buffer register */
/* bit 8 - 15 : reserved */
/* */
/* <P_PCI_TxBuf> */
/* bit 7 - 0 : PCITXBUF, PCI output buffer register */
/* bit 8 - 15 : reserved */
/*****************************************************************************/
typedef union
{
UInt16 W;
struct
{
UInt16 PCIRXBUF : 8;
UInt16 reserved : 8;
} B;
} P_PCI_RxBUF_DEF;
typedef union
{
UInt16 W;
struct
{
UInt16 PCITXBUF : 8;
UInt16 reserved : 8;
} B;
} P_PCI_TxBUF_DEF;
/*****************************************************************************/
/* H. Timer0/Timer1/Timer2 register */
/*****************************************************************************/
/*****************************************************************************/
/* Timer 0 control/status register (P_Timer0_Ctrl) */
/* bit 2 - 0 : CLKAFS, clock source A frequency selection */
/* = 000, CPUCLK / 2 */
/* = 001, CPUCLK / 256 */
/* = 010, 32768 Hz */
/* = 011, 8192 Hz */
/* = 100, 4096 Hz */
/* = 101, 1 */
/* = 110, 0 */
/* = 111, EXT1 */
/* bit 5 - 3 : CLKBFS, clock source B frequency selection */
/* = 000, 2048 Hz */
/* = 001, 1024 Hz */
/* = 010, 256 Hz */
/* = 011, TMB1 */
/* = 100, 4 Hz */
/* = 101, 2 Hz */
/* = 110, 1 */
/* = 111, EXT2 */
/* bit 6 : SYNCLK, the clock source of TMR0 is synchronized by CPUCLK */
/* = 1, synchronized */
/* = 0, non synchronized */
/* bit 10 - 7 : CCP0MS, Timer 0 CCP0 mode selection */
/* = 0000, capture/compare/PWM are off */
/* = 0100, capture mode, every falling edge */
/* = 0101, capture mode, every rising edge */
/* = 0110, capture mode, every 4 rising edge */
/* = 0111, capture mode, every 16 rising edge */
/* = 1000, compare mode, set output (CCP0IF set) */
/* = 1001, compare mode, clear output (CCP0IF set) */
/* = 101x, compare mode, CCP0 unaffected (CCP0IF set) */
/* = 1100, PWM mode, not return to one output (NRO) */
/* = 1101, PWM mode, not return to zero output (NRZ) */
/* = 1110, PWM mode, return to one output (RTO) */
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