📄 spmc70_regs.h
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/* ========================================================================= */
/* File Name : Spmc70_regs.h */
/* Description : SPMC70 series register definition */
/* Processor : SPMC701 */
/* Author : Chih ming Huang */
/* Date : February 2004 */
/* Tools : u'nSP IDE tools v1.14.X */
/* Version : 1.00 */
/* Security : Confidential Proprietary */
/* E-Mail : MaxHuang@sunplus.com.tw */
/* ========================================================================= */
#ifndef __SPMC70_REGS_H__
#define __SPMC70_REGS_H__
#include "Spmc_typedef.h"
/*****************************************************************************/
/* Selection body name of SPMC70 family */
/*****************************************************************************/
#define SPMC701FM0A
/*****************************************************************************/
/* A. CPU control register */
/*****************************************************************************/
#define P_Clk_Ctrl_ADDR 0x7069
#define P_System_Option_ADDR 0x8000
#define P_WatchDog_Ctrl_ADDR 0x7063
#define P_WatchDog_Clr_ADDR 0x7064
#define P_Reset_Status_ADDR 0x7065
/*****************************************************************************/
/* B. Flash organization and control register */
/*****************************************************************************/
#define P_Flash_RW_ADDR 0x7068
#define P_Flash_Ctrl_ADDR 0x7555
#define P_Wait_State_ADDR 0x706C
/*****************************************************************************/
/* C. Interrupt control register */
/*****************************************************************************/
#define P_INT_Ctrl_ADDR 0x7060
#define P_INT_Priority_ADDR 0x7061
#define P_INT_Status_ADDR 0x7062
#define P_TimeBase_Setup_ADDR 0x7040
#define P_TimeBase_Clr_ADDR 0x7041
/*****************************************************************************/
/* D. I/O Port register */
/*****************************************************************************/
#define P_IOA_Data_ADDR 0x7000
#define P_IOA_Buffer_ADDR 0x7001
#define P_IOA_Dir_ADDR 0x7002
#define P_IOA_Attrib_ADDR 0x7003
#define P_IOA_Latch_ADDR 0x7004
#define P_IOB_Data_ADDR 0x7008
#define P_IOB_Buffer_ADDR 0x7009
#define P_IOB_Dir_ADDR 0x700A
#define P_IOB_Attrib_ADDR 0x700B
#define P_IOB_Latch_ADDR 0x700C
#define P_IOC_Data_ADDR 0x7010
#define P_IOC_Buffer_ADDR 0x7011
#define P_IOC_Dir_ADDR 0x7012
#define P_IOC_Attrib_ADDR 0x7013
#define P_IOC_Latch_ADDR 0x7014
#define P_IOD_Data_ADDR 0x7018
#define P_IOD_Buffer_ADDR 0x7019
#define P_IOD_Dir_ADDR 0x701A
#define P_IOD_Attrib_ADDR 0x701B
#define P_IOD_Latch_ADDR 0x701C
/*****************************************************************************/
/* E. Low voltage reset and low voltage detection register */
/*****************************************************************************/
#define P_LVDLVR_Ctrl_ADDR 0x7066
#define P_LVD_Status_ADDR 0x7067
/*****************************************************************************/
/* F. Power saving modes and wakeup register */
/*****************************************************************************/
#define P_Wakeup_Source_ADDR 0x706A
#define P_Halt_Enter_ADDR 0x706E
#define P_Stdby_Enter_ADDR 0x706D
#define P_Wakeup_Status_ADDR 0x706F
#define P_Sleep_Enter_ADDR 0x706B
/*****************************************************************************/
/* G. Parallel Communication Interface register */
/*****************************************************************************/
#define P_PCI_Ctrl_ADDR 0x70C0
#define P_PCI_Status_ADDR 0x70C1
#define P_PCI_RxBuf_ADDR 0x70C2
#define P_PCI_TxBuf_ADDR 0x70C3
#define P_PCI_COMM_ADDR 0x70C4
/*****************************************************************************/
/* H. Timer 0, Timer 1, Timer 2 */
/*****************************************************************************/
#define P_Timer0_Ctrl_ADDR 0x7044
#define P_Timer0_Preload_ADDR 0x7045
#define P_Timer0_CCPR_ADDR 0x7046
#define P_Timer0_CCPR2_ADDR 0x7047
#define P_Timer1_Ctrl_ADDR 0x7048
#define P_Timer1_Preload_ADDR 0x7049
#define P_Timer1_CCPR_ADDR 0x704A
#define P_Timer1_CCPR2_ADDR 0x704B
#define P_Timer2_Ctrl_ADDR 0x704C
#define P_Timer2_Preload_ADDR 0x704D
/*****************************************************************************/
/* I. Standard Peripheral Interface SPI register */
/*****************************************************************************/
#define P_SPI_Ctrl_ADDR 0x7090
#define P_SPI_Status_ADDR 0x7091
#define P_SPI_TxBuf_ADDR 0x7092
#define P_SPI_RxBuf_ADDR 0x7092
/*****************************************************************************/
/* J. Serial input and output SIO register */
/*****************************************************************************/
#define P_SIO_Ctrl_ADDR 0x70B0
#define P_SIO_Status_ADDR 0x70B1
#define P_SIO_Buf_ADDR 0x70B2
#define P_SIO_Addr_ADDR 0x70B3
/*****************************************************************************/
/* K. Universal Asychronous Receiver/Transmitter UART register */
/*****************************************************************************/
#define P_UART_Ctrl_ADDR 0x70A0
#define P_UART_Status_ADDR 0x70A1
#define P_UART_Reset_ADDR 0x70A2
#define P_UART_BaudRateL_ADDR 0x70A3
#define P_UART_BaudRateH_ADDR 0x70A4
#define P_UART_TxBuf_ADDR 0x70A5
#define P_UART_RxBuf_ADDR 0x70A6
/*****************************************************************************/
/* L. 10-bit ADC converter register */
/*****************************************************************************/
#define P_ADC_Ctrl_ADDR 0x7070
#define P_ADC_Data_ADDR 0x7071
/*****************************************************************************/
/* Geneic register structure declaration */
/*****************************************************************************/
typedef union
{
UInt16 W;
struct
{
UInt16 bit0 : 1;
UInt16 bit1 : 1;
UInt16 bit2 : 1;
UInt16 bit3 : 1;
UInt16 bit4 : 1;
UInt16 bit5 : 1;
UInt16 bit6 : 1;
UInt16 bit7 : 1;
UInt16 bit8 : 1;
UInt16 bit9 : 1;
UInt16 bit10 : 1;
UInt16 bit11 : 1;
UInt16 bit12 : 1;
UInt16 bit13 : 1;
UInt16 bit14 : 1;
UInt16 bit15 : 1;
} B;
} GEN_REG_DEF;
/*****************************************************************************/
/* A. CPU control register */
/*****************************************************************************/
/*****************************************************************************/
/* Clock control register (P_Clk_Ctrl) */
/* bit 3 - 0 : CLKSEL, cpu clock selection */
/* = 000, 24 MHz (default) */
/* = 001, 48 MHz */
/* = 010, 12 MHz */
/* = 011, 6 MHz */
/* bit 4 - 15 : reserved */
/*****************************************************************************/
typedef union
{
UInt16 W;
struct
{
UInt16 CLKSEL : 3;
UInt16 reserved : 13;
} B;
} P_Clk_Ctrl_DEF;
/*****************************************************************************/
/* Watchdog control register (P_WatchDog_Ctrl) */
/* bit 0 : WDTENB, */
/* = 0, enable watchdog timer reset depends on WDG of */
/* information block */
/* = 1, disable watchdog timer reset */
/* bit 3 - 1 : WDTTMR, watchdog timer set */
/* = 111, 2683ms clear */
/* = 110, 1341ms clear */
/* = 101, 670ms clear */
/* = 100, 355ms clear */
/* = 011, 168ms clear */
/* = 010, 83840us clear */
/* = 001, 41920us clear */
/* = 000, 20960us clear */
/* bit 4 - 15 : reserved */
/*****************************************************************************/
typedef union
{
UInt16 W;
struct
{
UInt16 WDTENB : 1;
UInt16 WDTTMR : 3;
UInt16 reserved : 12;
} B;
} P_WatchDog_Ctrl_DEF;
/*****************************************************************************/
/* Reset status register (P_Reset_Status) */
/* bit 0 : EXTRST, external reset flag */
/* bit 1 : LVRST, low voltage reset flag */
/* bit 2 : WDTRST, watchdog timer reset flag */
/* bit 3 : ILLADDR, illegal address reset flag */
/* bit 4 : ICERST, ICE software reset flag */
/* bit 5 : PCIRST, reset from PCI */
/* bit 6 - 15 : reserved */
/*****************************************************************************/
typedef union
{
UInt16 W;
struct
{
UInt16 EXTRST : 1;
UInt16 LVRST : 1;
UInt16 WDTRST : 1;
UInt16 ILLADDR : 1;
UInt16 ICERST : 1;
UInt16 PCIRST : 1;
UInt16 reserved : 10;
} B;
} P_Reset_Status_DEF;
/*****************************************************************************/
/* C. Interrupt control register */
/*****************************************************************************/
/*****************************************************************************/
/* Interrupt control register (P_INT_Ctrl) */
/* bit 0 : 2HZIEN, 2Hz interrupt enable */
/* bit 1 : 4HZIEN, 4Hz interrupt enable */
/* bit 2 : TMB1IEN, timer base 1 interrupt enable */
/* bit 3 : TMB2IEN, timer base 2 interrupt enable */
/* bit 4 : KEYIEN, key-change interrupt enable */
/* bit 5 : EXT1IEDG, EXT1 interrupt trigger */
/* 1 = EXT1 interrupt trigger on rising edge */
/* 0 = EXT1 interrupt trigger on falling edge */
/* bit 6 : EXT2IEDG, EXT2 interrupt trigger */
/* 1 = EXT2 interrupt trigger on rising edge */
/* 0 = EXT2 interrupt trigger on falling edge */
/* bit 7 : EXT1IEN, EXT1 interrupt enable */
/* bit 8 : EXT2IEN, EXT2 interrupt enable */
/* bit 9 : EXT1INEN, EXT1 input enable */
/* bit 10 : EXT2INEN, EXT2 input enable */
/* bit 11 - 15: reserved */
/*****************************************************************************/
typedef union
{
UInt16 W;
struct
{
UInt16 _2HZIEN : 1;
UInt16 _4HZIEN : 1;
UInt16 TMB1IEN : 1;
UInt16 TMB2IEN : 1;
UInt16 KEYIEN : 1;
UInt16 EXT1IEDG : 1;
UInt16 EXT2IEDG : 1;
UInt16 EXT1IEN : 1;
UInt16 EXT2IEN : 1;
UInt16 EXT1INEN : 1;
UInt16 EXT2INEN : 1;
UInt16 reserved : 5;
} B;
} P_INT_Ctrl_DEF;
/*****************************************************************************/
/* IRQ and FIQ priority selection (P_INT_Priority) */
/* bit 0 - 3 : reserved */
/* bit 4 : KEYIP, key change interrupt priority */
/* 1 = FIQ, 0 = IRQ5 */
/* bit 5 : LVDIP, low voltage detect interrupt priority */
/* 1 = FIQ, 0 = IRQ5 */
/* bit 6 : TMR0IP, timer 0 interrupt priority */
/* 1 = FIQ, 0 = IRQ4 */
/* bit 7 : TMR1IP, timer 1 interrupt priority */
/* 1 = FIQ, 0 = IRQ4 */
/* bit 8 : TMR2IP, timer 2 interrupt priority */
/* 1 = FIQ, 0 = IRQ4 */
/* bit 9 : PCIIP, PCI interrupt priority */
/* 1 = FIQ, 0 = IRQ2 */
/* bit 10 : SIOIP, SIO interrupt priority */
/* 1 = FIQ, 0 = IRQ3 */
/* bit 11 : SPIIP, SPI interrupt priority */
/* 1 = FIQ, 0 = IRQ3 */
/* bit 12 : UARTIP, UART interrupt priority */
/* 1 = FIQ, 0 = IRQ3 */
/* bit 13 : EXT1IP, EXT1 interrupt priority */
/* 1 = FIQ, 0 = IRQ1 */
/* bit 14 : EXT2IP, EXT2 interrupt priority */
/* 1 = FIQ, 0 = IRQ1 */
/* bit 15 : ADCIP, ADC interrupt priority */
/* 1 = FIQ, 0 = IRQ0 */
/*****************************************************************************/
typedef union
{
UInt16 W;
struct
{
UInt16 reserved : 4;
UInt16 KEYIP : 1;
UInt16 LVDIP : 1;
UInt16 TMR0IP : 1;
UInt16 TMR1IP : 1;
UInt16 TMR2IP : 1;
UInt16 PCIIP : 1;
UInt16 SIOIP : 1;
UInt16 SPIIP : 1;
UInt16 UARTIP : 1;
UInt16 EXT1IP : 1;
UInt16 EXT2IP : 1;
UInt16 ADCIP : 1;
} B;
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