spmc75_regs.h

基于SPMC75的变频电机驱动例子,相当于一个简单的变频器. 望对变频器开发的工程式师有一定的帮助!

/* bit 14    	: V2NEN, V2N phase output enable							 */		
/* bit 15    	: W2NEN, W2N phase output enable							 */		
/*****************************************************************************/
typedef union
{
	UInt16	W;
	struct
	{
		UInt16	Reserve1	: 2;
		UInt16	EXINT0EN	: 1;
		UInt16	EXINT1EN	: 1;
		UInt16	Reserve2	: 1;		
		UInt16	TIO1AEN		: 1;
		UInt16	TIO1BEN		: 1;
		UInt16	TIO1CEN		: 1;	
		UInt16	OL2EN		: 1;
		UInt16	FTIN2EN		: 1;		
		UInt16	U2EN		: 1;
		UInt16	V2EN		: 1;
		UInt16	W2EN		: 1;
		UInt16	U2NEN		: 1;
		UInt16	V2NEN		: 1;
		UInt16	W2NEN		: 1;					
	} B;	
} P_IOC_SPE_DEF;

/*****************************************************************************/
/* IOA  Keychange Enable Control Register (P_IOA_KCER)				 		 */
/* bit 7 - 0    : Reserve													 */
/* bit 8    	: KC8EN, PortA.8 Key change enable						 	 */											 
/* bit 9    	: KC9EN, PortA.9 Key change enable						 	 */	
/* bit 10    	: KC10EN, PortA.10 Key change enable						 */	
/* bit 11    	: KC11EN, PortA.11 Key change enable						 */	
/* bit 12    	: KC12EN, PortA.12 Key change enable						 */	
/* bit 13    	: KC13EN, PortA.13 Key change enable						 */	
/* bit 14    	: KC14EN, PortA.14 Key change enable						 */	
/* bit 15    	: KC15EN, PortA.15 Key change enable						 */	
/*****************************************************************************/
typedef union
{
	UInt16	W;
	struct
	{
		UInt16	Reserve1	: 8;
		UInt16	KC8EN		: 1;
		UInt16	KC9EN		: 1;
		UInt16	KC10EN		: 1;
		UInt16	KC11EN		: 1;
		UInt16	KC12EN		: 1;
		UInt16	KC13EN		: 1;
		UInt16	KC14EN		: 1;
		UInt16	KC15EN		: 1;												
	} B;	
} P_IOA_KCER_DEF;

/*****************************************************************************/
/*****************************************************************************/
/* C. Timer0/Timer1/Timer2/Timer3/Timer4 register							 */
/*****************************************************************************/
/*****************************************************************************/
/* Timer 0 controlregister (P_TMR0_Ctrl)								     */
/* Timer 1 controlregister (P_TMR1_Ctrl)									 */
/* Timer 2 controlregister (P_TMR2_Ctrl)									 */
/* bit 2 - 0    : TMRPS, clock source A frequency selection					 */
/*				= 000, Counts on FCK /1										 */
/*				= 001, Counts on FCK /4										 */		
/*				= 010, Counts on FCK /16									 */	
/*				= 011, Counts on FCK /64									 */
/*				= 100, Counts on FCK /256									 */
/*				= 101, Counts on FCK /1024									 */
/*				= 110, Counts on TCLKA pin input 							 */
/*				= 111, Counts on TCLKB pin input 							 */
/* bit 4 - 3    : CKEGS, Clock edge select									 */											 
/*				= 00, Count at rising edge									 */	
/*				= 01, Count at falling edge									 */
/*				= 1X, Count at both edges 									 */
/* bit 7 - 5    : CCLS, Counter clear source select							 */	
/*				= 000, TCNT clearing disabled								 */
/*				= 001, TCNT cleared by TGRA capture input					 */
/*				= 010, TCNT cleared by TGRB capture input					 */
/*				= 011, TCNT cleared by TGRC capture input					 */
/*				= 100, TCNT cleared by every PDR change 6 times				 */
/*				= 101, TCNT cleared by every PDR change 3 times				 */	
/*				= 110, TCNT cleared by P_POS0/1_Data change			 		 */
/*				= 111, TCNT cleared by P_TMR1/2_TPR compare match		 	 */
/* bit 9 - 8    : CLEGS, Counter clear edge select. 						 */
/*				= 00, do not clear											 */
/*				= 01, rising edge											 */
/*				= 10, falling edge											 */		
/*				= 11, both edge												 */
/* bit 13 - 10  : MODE, select the timer operation modes					 */
/*				= 0000, Normal operation 									 */
/*				  (counter up-counting, compare match output mode)			 */
/*				= 0100, Phase counting mode 1 								 */
/*				= 0101, Phase counting mode 2 								 */
/*				= 0110, Phase counting mode 3 								 */
/*				= 0111, Phase counting mode 4 								 */	
/*				= 1x0x, Edge-aligned PWM mode (counter up-count, PWM output) */
/*				= 1x1x, Center-aligned PWM mode 					         */
/*				  (counter continuous up-/down-count, PWM output)	         */
/* bit 15 - 14  : SPCK, Capture input sample clock select					 */
/*				= 00, FCK/1													 */		
/*				= 01, FCK/2													 */		
/*				= 10, FCK/4													 */		
/*				= 11, FCK/8													 */		
/*****************************************************************************/
typedef union
{
	UInt16	W;
	struct
	{
		UInt16	TMRPS		: 3;
		UInt16	CKEGS		: 2;
		UInt16	CCLS		: 3;
		UInt16	CLEGS		: 2;
		UInt16	MODE		: 4;
		UInt16	SPCK		: 2;
	} B;	
} P_TMR0_Ctrl_DEF;
typedef union
{
	UInt16	W;
	struct
	{
		UInt16	TMRPS		: 3;
		UInt16	CKEGS		: 2;
		UInt16	CCLS		: 3;
		UInt16	CLEGS		: 2;
		UInt16	MODE		: 4;
		UInt16	SPCK		: 2;
	} B;	
} P_TMR1_Ctrl_DEF;
typedef union
{
	UInt16	W;
	struct
	{
		UInt16	TMRPS		: 3;
		UInt16	CKEGS		: 2;
		UInt16	CCLS		: 3;
		UInt16	CLEGS		: 2;
		UInt16	MODE		: 4;
		UInt16	SPCK		: 2;
	} B;	
} P_TMR2_Ctrl_DEF;
/*****************************************************************************/
/* Timer 3 control register (P_TMR3_Ctrl)									 */	
/* Timer 4 control register (P_TMR4_Ctrl)									 */
/* bit 2 - 0	: TMRPS, clock source A frequency selection					 */
/*				= 000, Counts on FCK /1										 */		
/*				= 001, Counts on FCK /4										 */	
/*				= 010, Counts on FCK /16									 */
/*				= 011, Counts on FCK /64									 */
/*				= 100, Counts on FCK /256									 */
/*				= 101, Counts on FCK /1024									 */	
/*				= 110, Counts on TCLKA pin input 							 */
/*				= 111, Counts on TCLKB pin input 							 */
/* bit 4 - 3	: CKEGS, Clock edge select									 */											 
/*				= 00, Count at rising edge									 */
/*				= 01, Count at falling edge									 */	
/*				= 1X, Count at both edges 									 */
/* bit 7 - 5	: CCLS, Counter clear source select							 */	
/*				= 000, TCNT clearing disabled								 */	
/*				= 001, Reserved												 */
/*				= 010, Reserved												 */	
/*				= 011, Reserved												 */	
/*				= 011, Reserved												 */			
/*				= 100, Reserved											     */
/*				= 101, Reserved												 */	
/*				= 111, TCNT cleared by P_TMR3/4_TPR compare match			 */
/* bit 9:8		: Reserve													 */
/* bit 13 - 10	: MODE, timer mode selection								 */
/*				= 0xxx, Normal operation 									 */
/*				  (counter up-counting, compare match output mode)			 */
/*				= 1x0x, Edge-aligned PWM mode (counter up-count, PWM output) */
/*				= 1x1x, Center-aligned PWM mode 							 */
/*				  (counter continuous up-/down-count, PWM output)	  		 */
/* bit 15 - 14	: PRDINT,  TPR interrupt frequency select					 */
/*				= 00, Interrupt every period								 */
/*				= 01, Interrupt once every 2 periods						 */	
/*				= 10, Interrupt once every 4 periods						 */
/*				= 11, Interrupt once every 8 periods						 */			
/*****************************************************************************/
typedef union
{
	UInt16	W;
	struct
	{
		UInt16	TMRPS		: 3;
		UInt16	CKEGS		: 2;
		UInt16	CCLS		: 3;
		UInt16	Reserved	: 2;
		UInt16	MODE		: 4;
		UInt16	PRDINT		: 2;
	} B;	
} P_TMR3_Ctrl_DEF;
typedef union
{
	UInt16	W;
	struct
	{
		UInt16	TMRPS		: 3;
		UInt16	CKEGS		: 2;
		UInt16	CCLS		: 3;
		UInt16	Reserved	: 2;
		UInt16	MODE		: 4;
		UInt16	PRDINT		: 2;
	} B;	
} P_TMR4_Ctrl_DEF;

/*****************************************************************************/
/* Timer TMR Load Ok (P_TMR_LDOK)									 		 */	
/* bit 0		: LDOK0, P_TMR3_TGRA-C ok to load bit					 	 */
/* bit 1		: LDOK1, P_TMR4_TGRA-C ok to load bit						 */											 
/* bit 7 - 2	: TLDCHK, Timer load register check bits					 */	
/* bit 15:8		: Reserve													 */	
/*****************************************************************************/
typedef union
{
	UInt16	W;
	struct
	{
		UInt16	LDOK0		: 1;
		UInt16	LDOK1		: 1;
		UInt16	TLDCHK		: 6;
		UInt16	Reserved	: 8;
	} B;	
} P_TMR_LDOK_DEF;

/*****************************************************************************/
/* Timer 0/1 IO Control register (P_TMR0/1_IOCtrl)							 */
/* bit 3 - 0   : IOAMODE, Select Timer0/1 IOA Configurartion 				 */
/* bit 7 - 4   : IOBMODE, Select Timer0/1 IOB Configurartion 				 */
/* bit 11 - 8  : IOCMODE, Select Timer0/1 IOC Configurartion 				 */
/*				Compare Mode:												 */
/*				= 0000, Initial output 0, 0 output at compare match			 */
/*				= 0001, Initial output 0, 1 output at compare match			 */
/*				= 0010, Initial output 1, 0 output at compare match			 */
/*				= 0011, Initial output 1, 1 output at compare match			 */
/*				= 01xx, Output hold											 */
/*				Capture Mode												 */
/*				= 1000, Issue input capture interrupt at rising edge		 */
/*				= 1001, Issue input capture interrupt at falling edge		 */
/*				= 101x, Issue input capture interrupt at both edges			 */
/*				= 11xx, Input capture when Position Detection Register 		 */
/*				  changes (capture Timer Counter Register value 			 */
/*				  to Timer General Register) and issue interrupt 			 */
/*				  (for Timer General A Register only)						 */
/* bit 15 - 12 : Reserve												 	 */
/*****************************************************************************/
typedef union
{
	UInt16	W;
	struct
	{
		UInt16	IOAMODE		: 4;
		UInt16	IOBMODE		: 4;
		UInt16	IOCMODE		: 4;
		UInt16	Reserved	: 4;	
	} B;
} P_TMR0_IOCtrl_DEF;
typedef union
{
	UInt16	W;
	struct
	{
		UInt16	IOAMODE		: 4;
		UInt16	IOBMODE		: 4;
		UInt16	IOCMODE		: 4;
		UInt16	Reserved	: 4;	
	} B;
} P_TMR1_IOCtrl_DEF;
/*****************************************************************************/
/* Timer 2 IO Control register (P_TMR2_IOCtrl)								 */
/* bit 3 - 0  : IOAMODE, Select Timer2 IOA Configurartion 					 */
/* bit 7 - 4  : IOBMODE, Select Timer2 IOB Configurartion 					 */						
/* bit 15 - 8 : Reserved													 */
/*				Compare Mode:												 */
/*				= 0000, Initial output 0, 0 output at compare match			 */
/*				= 0001, Initial output 0, 1 output at compare match			 */
/*				= 0010, Initial output 1, 0 output at compare match			 */
/*				= 0011, Initial output 1, 1 output at compare match			 */
/*				= 01xx, Output hold											 */
/*				Capture Mode												 */
/*				= 1000, Issue input capture interrupt at rising edge		 */
/*				= 1001, Issue input capture interrupt at falling edge		 */
/*				= 101x, Issue input capture interrupt at both edges			 */
/*				= 11xx, Reserve									 			 */
/*****************************************************************************/
typedef union
{
	UInt16	W;
	struct
	{
		UInt16	IOAMODE		: 4;
		UInt16	IOBMODE		: 4;
		UInt16	Reserved	: 8;	
	} B;
} P_TMR2_IOCtrl_DEF;

/*****************************************************************************/
/* Timer 3/4 IO Control register (P_TMR3/4_IOCtrl)							 */
/* bit 3 - 0  : IOAMODE, Select Timer3/4 IOA Configurartion 				 */
/* bit 7 - 4  : IOBMODE, Select Timer3/4 IOB Configurartion 				 */
/* bit 11 - 8 : IOCMODE, Select Timer3/4 IOC Configurartion 				 */
/* 				Compare Mode,												 */
/*				= 0000, Initial output 0, 0 output at compare match			 */
/*				= 0001, Initial output 0, 1 output at compare match			 */
/*				= 0010, Initial output 1, 0 output at compare match			 */
/*				= 0011, Initial output 1, 1 output at compare match			 */
/*				= 01xx, Output hold											 */
/*				= 1xxx, Reserve								 				 */
/* bit 12 - 15: Reserved													 */
/*****************************************************************************/
typedef union
{
	UInt16	W;
	struct
	{
		UInt16	IOAMODE		: 4;
		UInt16	IOBMODE		: 4;
		UInt16	IOCMODE		: 4;
		UInt16	Reserved	: 4;	
	} B;
} P_TMR3_IOCtrl_DEF;
typedef union
{
	UInt16	W;
	struct
	{
		UInt16	IOAMODE		: 4;
		UInt16	IOBMODE		: 4;
		UInt16	IOCMODE		: 4;
		UInt16	Reserved	: 4;	
	} B;
} P_TMR4_IOCtrl_DEF;
/*****************************************************************************/
/* Timer 0/1 Interrupt Enable Register (P_TMR0/1_INT)						 */
/* bit 0  	: TGAIE, Timer General A Register interrupt enable bit			 */
/* bit 1  	: TGBIE, Timer General B Register interrupt enable bit			 */
/* bit 2  	: TGCIE, Timer General C Register interrupt enable bit			 */
/* bit 3  	: Reserve														 */
/* bit 4  	: TPRIE, Timer Period Register interrupt enable bit				 */
/* bit 5  	: TCVIE, Overflow interrupt enable bit							 */
/* bit 6  	: TCUIE, Underflow interrupt enable bit							 */
/* bit 7  	: TADSE, A/D conversion start request enable bit				 */
/* bit 8  	: PDCIE, Position detection change interrupt enable bit			 */
/* bit 9:15	: Reserve													  	 */
/*****************************************************************************/
typedef union
{
	UInt16	W;
	struct
	{
		UInt16	TGAIE		: 1;
		UInt16	TGBIE		: 1;
		UInt16	TGCIE		: 1;
		UInt16	Reserved1	: 1;	
		UInt16  TPRIE		: 1;
		UInt16  TCVIE      	: 1;
		UInt16  TCUIE		: 1;
		UInt16  TADSE		: 1;
		UInt16  PDCIE		: 1; 	
		UInt16  Reserved2 	: 7; 	
	} B;
} P_TMR0_INT_DEF;
typedef union
{
	UInt16	W;
	struct
	{
		UInt16	TGAIE		: 1;
		UInt16	TGBIE		: 1;
		UInt16	TGCIE		: 1;
		UInt16	Reserved1	: 1;