spmc75_regs.h

基于sunplus的16MCU产品,SPMC75的键盘和显示的例子,完整的工程,对单片机开发工程式师有一定的借鉴作用.

/* ========================================================================= */
/* File Name   : Spmc75_regs.h										     	 */	
/* Description : SPMC75 series register definition						     */
/* Processor   : SPMC75F													 */	
/* Author      : Sunplus SA7											     */
/* Date        : May 2004											     	 */
/* Tools	   : u'nSP IDE tools v1.15.x 								     */
/* Version     : 1.00 													     */	
/* Security    : Confidential Proprietary 							         */
/* Updata	   : 2004/6/28													 */
/* 			   : PDR Change													 */
/* ========================================================================= */
#ifndef	__SPMC75_REGS_H
#define	__SPMC75_REGS_H

#include "Spmc_typedef.h"

/*****************************************************************************/
/* Selection body name of SPMC75 family										 */
/*****************************************************************************/
#define SPMC75F2413A

/*****************************************************************************/
/* Register word and bit code debug mode definition, enable or not			 */
/*****************************************************************************/
//#define SPMC75_REG_DEBUG

/*****************************************************************************/
/*****************************************************************************/
/* A. CPU control register													 */
/*****************************************************************************/
/*****************************************************************************/
#define P_System_Option_ADDR			0x8000	
#define P_Wait_Enter_ADDR				0x700C
#define P_Stdby_Enter_ADDR				0x700E
#define P_Reset_Status_ADDR				0x7006
#define P_Clk_Ctrl_ADDR					0x7007
#define P_WatchDog_Ctrl_ADDR			0x700A
#define P_WatchDog_Clr_ADDR				0x700B
#define	P_Wakeup_Ctrl_ADDR				0x700F
#define P_INT_Status_ADDR				0x70A0
#define P_INT_Priority_ADDR				0x70A4
#define P_MisINT_Ctrl_ADDR				0x70A8

/*****************************************************************************/
/*****************************************************************************/
/* B. I/O Port register														 */
/*****************************************************************************/
/*****************************************************************************/
#define P_IOA_Data_ADDR					0x7060
#define P_IOA_Buffer_ADDR				0x7061
#define P_IOA_Dir_ADDR					0x7062
#define P_IOA_Attrib_ADDR				0x7063
#define P_IOA_Latch_ADDR				0x7064
#define P_IOA_SPE_ADDR					0x7080
#define	P_IOA_KCER_ADDR					0x7084

#define P_IOB_Data_ADDR					0x7068
#define P_IOB_Buffer_ADDR				0x7069
#define P_IOB_Dir_ADDR					0x706A
#define P_IOB_Attrib_ADDR				0x706B
#define P_IOB_SPE_ADDR					0x7081

#define P_IOC_Data_ADDR					0x7070
#define P_IOC_Buffer_ADDR				0x7071
#define P_IOC_Dir_ADDR					0x7072
#define P_IOC_Attrib_ADDR				0x7073
#define P_IOC_SPE_ADDR					0x7082

#define P_IOD_Data_ADDR					0x7078
#define P_IOD_Buffer_ADDR				0x7079
#define P_IOD_Dir_ADDR					0x707A
#define P_IOD_Attrib_ADDR				0x707B

/*****************************************************************************/
/*****************************************************************************/
/* C. Timer 0,Timer 1,Timer 2,Timer 3,Timer 4								 */
/*****************************************************************************/
/*****************************************************************************/
#define P_TMR0_Ctrl_ADDR			0x7400
#define P_TMR1_Ctrl_ADDR			0x7401
#define P_TMR2_Ctrl_ADDR			0x7402
#define P_TMR3_Ctrl_ADDR			0x7403
#define P_TMR4_Ctrl_ADDR			0x7404

#define P_TMR_LDOK_ADDR				0x740A

#define P_TMR0_TCNT_ADDR			0x7430
#define P_TMR1_TCNT_ADDR			0x7431
#define P_TMR2_TCNT_ADDR			0x7432
#define P_TMR3_TCNT_ADDR			0x7433
#define P_TMR4_TCNT_ADDR			0x7434

#define P_TMR0_TGRA_ADDR			0x7440
#define P_TMR0_TGRB_ADDR			0x7441
#define P_TMR0_TGRC_ADDR			0x7442

#define P_TMR1_TGRA_ADDR			0x7443
#define P_TMR1_TGRB_ADDR			0x7444
#define P_TMR1_TGRC_ADDR			0x7445

#define P_TMR2_TGRA_ADDR			0x7446
#define P_TMR2_TGRB_ADDR			0x7447

#define P_TMR3_TGRA_ADDR			0x7448
#define P_TMR3_TGRB_ADDR			0x7449
#define P_TMR3_TGRC_ADDR			0x744A
#define P_TMR3_TGRD_ADDR			0x744B

#define P_TMR4_TGRA_ADDR			0x744C
#define P_TMR4_TGRB_ADDR			0x744D
#define P_TMR4_TGRC_ADDR			0x744E
#define P_TMR4_TGRD_ADDR			0x744F

#define P_TMR0_TPR_ADDR				0x7435
#define P_TMR1_TPR_ADDR				0x7436
#define P_TMR2_TPR_ADDR				0x7437
#define P_TMR3_TPR_ADDR				0x7438
#define P_TMR4_TPR_ADDR				0x7439

#define P_TMR0_TBRA_ADDR			0x7450
#define P_TMR0_TBRB_ADDR			0x7451
#define P_TMR0_TBRC_ADDR			0x7452

#define P_TMR1_TBRA_ADDR			0x7453
#define P_TMR1_TBRB_ADDR			0x7454
#define P_TMR1_TBRC_ADDR			0x7455

#define P_TMR2_TBRA_ADDR			0x7456
#define P_TMR2_TBRB_ADDR			0x7457

#define P_TMR3_TBRA_ADDR			0x7458
#define P_TMR3_TBRB_ADDR			0x7459
#define P_TMR3_TBRC_ADDR			0x745A

#define P_TMR4_TBRA_ADDR			0x745C
#define P_TMR4_TBRB_ADDR			0x745D
#define P_TMR4_TBRC_ADDR			0x745E

#define	P_TMR0_IOCtrl_ADDR			0x7410
#define	P_TMR1_IOCtrl_ADDR			0x7411
#define	P_TMR2_IOCtrl_ADDR			0x7412
#define	P_TMR3_IOCtrl_ADDR			0x7413
#define	P_TMR4_IOCtrl_ADDR			0x7414

#define P_TMR0_INT_ADDR				0x7420
#define P_TMR1_INT_ADDR				0x7421
#define P_TMR2_INT_ADDR				0x7422
#define P_TMR3_INT_ADDR				0x7423
#define P_TMR4_INT_ADDR				0x7424

#define P_TMR0_Status_ADDR			0x7425
#define P_TMR1_Status_ADDR			0x7426
#define P_TMR2_Status_ADDR			0x7427
#define P_TMR3_Status_ADDR			0x7428
#define P_TMR4_Status_ADDR			0x7429

#define P_TMR_Start_ADDR			0x7405
#define P_TMR_Output_ADDR			0x7406

#define P_TMR3_OutputCtrl_ADDR		0x7407
#define P_TMR4_OutputCtrl_ADDR		0x7408

#define	P_POS0_DectCtrl_ADDR		0x7462
#define	P_POS1_DectCtrl_ADDR		0x7463

#define	P_POS0_DectData_ADDR		0x7464
#define	P_POS1_DectData_ADDR		0x7465

#define	P_TMR3_DeadTime_ADDR		0x7460
#define	P_TMR4_DeadTime_ADDR		0x7461

#define	P_TPWM_Write_ADDR			0x7409

#define	P_Fault1_Ctrl_ADDR			0x7466
#define	P_Fault2_Ctrl_ADDR			0x7467

#define	P_OL1_Ctrl_ADDR				0x7468
#define	P_OL2_Ctrl_ADDR				0x7469

#define	P_Fault1_Release_ADDR		0x746A
#define	P_Fault2_Release_ADDR		0x746B

/*****************************************************************************/
/*****************************************************************************/
/* D. 10-bit ADC converter register											 */
/*****************************************************************************/
/*****************************************************************************/
#define P_ADC_Setup_ADDR				0x7160
#define P_ADC_Ctrl_ADDR					0x7161
#define P_ADC_Data_ADDR					0x7162
#define P_ADC_Channel_ADDR				0x7166

/*****************************************************************************/
/*****************************************************************************/
/* E. Standard Peripheral Interface  SPI register							 */
/*****************************************************************************/
/*****************************************************************************/
#define P_SPI_Ctrl_ADDR					0x7140
#define P_SPI_TxStatus_ADDR				0x7141
#define P_SPI_TxBuf_ADDR				0x7142
#define P_SPI_RxStatus_ADDR				0x7143
#define P_SPI_RxBuf_ADDR				0x7144

/*****************************************************************************/
/*****************************************************************************/
/* F. Flash organization and control register								 */
/*****************************************************************************/
/*****************************************************************************/
#define P_Flash_RW_ADDR					0x704D	
#define P_Flash_Ctrl_ADDR				0x7555

/*****************************************************************************/
/*****************************************************************************/
/* G. UART Control Register													 */
/*****************************************************************************/
/*****************************************************************************/
#define P_UART_Data_ADDR				0x7100	
#define P_UART_RXStatus_ADDR			0x7101	
#define P_UART_Ctrl_ADDR				0x7102	
#define P_UART_BaudRate_ADDR			0x7103	
#define P_UART_Status_ADDR				0x7104	

/*****************************************************************************/
/*****************************************************************************/
/* H. Compare Match Timer Register											 */				
/*****************************************************************************/
/*****************************************************************************/
#define P_CMT_Start_ADDR				0x7500
#define P_CMT_Ctrl_ADDR					0x7501
#define P_CMT0_TCNT_ADDR				0x7508
#define P_CMT1_TCNT_ADDR				0x7509
#define P_CMT0_TPR_ADDR					0x7510
#define P_CMT1_TPR_ADDR					0x7511	

/*****************************************************************************/
/*****************************************************************************/
/* I. Time Base Register													 */				
/*****************************************************************************/
/*****************************************************************************/
#define P_TMB_Reset_ADDR				0x70B8
#define P_BZO_Ctrl_ADDR					0x70B9

/*****************************************************************************/
/* Geneic register structure declaration									 */
/*****************************************************************************/
typedef union
{
	UInt16	W;
	struct
	{
		UInt16	bit0		: 1;
		UInt16	bit1		: 1;
		UInt16	bit2		: 1;
		UInt16	bit3		: 1;
		UInt16	bit4		: 1;
		UInt16	bit5		: 1;
		UInt16	bit6		: 1;
		UInt16	bit7		: 1;
		UInt16	bit8		: 1;
		UInt16	bit9		: 1;
		UInt16	bit10		: 1;
		UInt16	bit11		: 1;
		UInt16	bit12		: 1;
		UInt16	bit13		: 1;
		UInt16	bit14		: 1;
		UInt16	bit15		: 1;
	} B;
} GEN_REG_DEF;

/*****************************************************************************/
/*****************************************************************************/
/* A. CPU Control Register						 							 */
/*****************************************************************************/
/*****************************************************************************/
typedef union
{
	UInt16	W;
	struct
	{
		UInt16	WaitCMD		: 16;
	} B;	
} P_Wait_Enter_DEF;

typedef union
{
	UInt16	W;
	struct
	{
		UInt16	StdbyCMD	: 16;
	} B;	
} P_Stdby_Enter_DEF;

/*****************************************************************************/
/*****************************************************************************/
/* B. IO Control Register						 							 */
/*****************************************************************************/
/*****************************************************************************/
/*****************************************************************************/
/* IOA Special Functions Enable Control Register (P_IOA_SPE)				 */
/* bit 8 - 0    : Reserve													 */
/* bit 9    	: TIO2AEN, P_TMR2_TGRA CCP enable							 */											 
/* bit 10    	: TIO2BEN, P_TMR2_TGRB CCP enable							 */
/* bit 11		: TCLKAEN, External clock A input pin enable				 */
/* bit 12		: TCLKBEN, External clock B input pin enable				 */
/* bit 13		: TCLKCEN, External clock C input pin enable				 */
/* bit 14		: TCLKDEN, External clock D input pin enable				 */
/* bit 15 		: Reserve													 */
/*****************************************************************************/
typedef union
{
	UInt16	W;
	struct
	{
		UInt16	Reserve1	: 9;
		UInt16	TIO2AEN		: 1;
		UInt16	TIO2BEN		: 1;		
		UInt16	TCLKAEN		: 1;
		UInt16	TCLKBEN		: 1;
		UInt16	TCLKCEN		: 1;
		UInt16	TCLKDEN		: 1;
		UInt16	Reserve2	: 1;				
	} B;	
} P_IOA_SPE_DEF;

/*****************************************************************************/
/* IOB Special Functions Enable Control Register (P_IOB_SPE)				 */
/* bit 0    	: W1NEN,  W1N phase output enable							 */
/* bit 1    	: V1NEN,  V1N phase output enable							 */
/* bit 2    	: U1NEN,  U1N phase output enable							 */
/* bit 3    	: W1EN,  W1 phase output enable							 	 */
/* bit 4    	: V1EN,  V1 phase output enable							 	 */
/* bit 5    	: U1EN,  U1 phase output enable							 	 */
/* bit 6    	: FTIN1EN, External fault protection input 1 enable			 */										 
/* bit 7    	: OL1EN, Overload protection input 1 enable					 */
/* bit 8		: TIO0CEN, P_TMR0_TGRC CCP enable				 			 */
/* bit 9		: TIO0BEN, P_TMR0_TGRB CCP enable				 			 */
/* bit 10		: TIO0AEN, P_TMR0_TGRA CCP enable				 			 */
/* bit 15 - 11	: Reserve													 */
/*****************************************************************************/
typedef union
{
	UInt16	W;
	struct
	{
		UInt16	W1NEN		: 1;
		UInt16	V1NEN		: 1;
		UInt16	U1NEN		: 1;
		UInt16	W1EN		: 1;
		UInt16	V1EN		: 1;
		UInt16	U1EN		: 1;	
		UInt16	FTIN1EN		: 1;
		UInt16	OL1EN		: 1;		
		UInt16	TIO0CEN		: 1;
		UInt16	TIO0BEN		: 1;
		UInt16	TIO0AEN		: 1;
		UInt16	Reserve		: 5;				
	} B;	
} P_IOB_SPE_DEF;

/*****************************************************************************/
/* IOC Special Functions Enable Control Register (P_IOC_SPE)				 */
/* bit 1 - 0	: Reserve													 */
/* bit 2    	: EXINT0EN,  External interrupt input 0 enable 				 */
/* bit 3    	: EXINT1EN,  External interrupt input 1 enable				 */
/* bit 4    	: Reserve													 */
/* bit 5    	: TIO1AEN,  P_TMR1_TGRA	CCP enable						 	 */
/* bit 6    	: TIO1BEN,  P_TMR1_TGRB	CCP enable						 	 */
/* bit 7    	: TIO1CEN,  P_TMR1_TGRC	CCP enable						 	 */
/* bit 8    	: OL2EN,  Overload protection input 2 enable			 	 */
/* bit 9    	: FTIN2EN,  External fault protection input 2 enable	 	 */
/* bit 10    	: U2EN, U2 phase output enable								 */										 
/* bit 11    	: V2EN, V2 phase output enable								 */		
/* bit 12    	: W2EN, W2 phase output enable								 */		
/* bit 13    	: U2NEN, U2N phase output enable							 */