adsp-bf561_c.ldf

BlackFin LCD 显示, 简单GUI图形显示

#define CRT  crtsf561y.doj
#else
#define CRT  crtsf561.doj
#endif	/* } */
#endif /* __cplusplus */	/* } */
#else
#ifdef __cplusplus	/* { */
#ifdef __WORKAROUNDS_ENABLED	/* { */
#define CRT  crtsc561y.doj
#else
#define CRT  crtsc561.doj
#endif	/* } */
#else
#ifdef __WORKAROUNDS_ENABLED	/* { */
#define CRT	crts561y.doj
#else
#define CRT	crts561.doj
#endif	/* } */
#endif /* __cplusplus */	/* } */
#endif  /* USE_FILEIO */	/* } */
#endif  /* USE_PROFILER */	/* } */
#endif /* USER_CRT } */

#ifdef __cplusplus	/* { */
#ifdef __WORKAROUNDS_ENABLED	/* { */
#define ENDCRT , crtn561y.doj
#else
#define ENDCRT , crtn561.doj
#endif	/* } */
#else
#define ENDCRT
#endif	/* } */
$OBJECTS_CORE_A = CRT, $COMMAND_LINE_OBJECTS ,cplbtab561a.doj ENDCRT;
$OBJECTS_CORE_B = CRT, $COMMAND_LINE_OBJECTS ,cplbtab561b.doj ENDCRT;
$OBJECTS = $COMMAND_LINE_OBJECTS;


MEMORY
 /* L2 SRAM - 128K. */{
//MEM_L2_SRAM    { START(0xFEB00000) END(0xFEB1FFFF) TYPE(RAM) WIDTH(8) }
MEM_L2_SRAM     {	TYPE(RAM) WIDTH(8)	START(0xFEB00000) END(0xFEB0ffff) }
 /* Async Memory in Banks of 64 MB */
MEM_ASYNC3     { START(0x2C000000) END(0x2FFFFFFF) TYPE(RAM) WIDTH(8) }
MEM_ASYNC2     { START(0x28000000) END(0x2BFFFFFF) TYPE(RAM) WIDTH(8) }
MEM_ASYNC1     { START(0x24000000) END(0x27FFFFFF) TYPE(RAM) WIDTH(8) }
MEM_ASYNC0     { START(0x20000000) END(0x23FFFFFF) TYPE(RAM) WIDTH(8) }

/* Claim some of SDRAM Bank 0 for heap */
/* since it needs a separate section */
#if !defined(PARTITION_EZKIT_SDRAM)
# define PARTITION_EZKIT_SDRAM
#endif
MEM_SDRAM0_BANK3  { START(0x03000000) END(0x03FFFFFF) TYPE(RAM) WIDTH(8) }
MEM_SDRAM0_BANK2  { START(0x02000000) END(0x02FFFFFF) TYPE(RAM) WIDTH(8) }
MEM_SDRAM0_BANK1  { START(0x01000000) END(0x01FFFFFF) TYPE(RAM) WIDTH(8) }
/*  Declare heap for both cores in bank 0. If __ADI_MULTICORE is
 ** defined we use a shared heap. If not, each core has it's own space.
 */
#if defined(__ADI_MULTICORE)
/*  16 MB Heap is to be shared between both cores. It must reside in a
 ** Shared memory location, and can only be accessed using the
 ** re-entrant safe libraries.
 */
MEM_SDRAM0_HEAP   { START(0x00000004) END(0x00FFFFFF) TYPE(RAM) WIDTH(8) }
}
#else
/*  A separate 8 MB heapspace is allocated for each core.
 ** The heaps should only be accessed by the correct core.
 ** Re-entrant safe libraries do not need to be used.
 */
MEM_SDRAM0_HEAP_A { START(0x00000004) END(0x007FFFFF) TYPE(RAM) WIDTH(8) }
MEM_SDRAM0_HEAP_B { START(0x00800000) END(0x00FFFFFF) TYPE(RAM) WIDTH(8) }
#endif
}
SHARED_MEMORY
{
	RESOLVE(_Image_BMP,  0x0010C400)
	RESOLVE(_PingFrame , 0x01000000)
	RESOLVE(_PongFrame , 0x02000000)


	OUTPUT($COMMAND_LINE_OUTPUT_DIRECTORY/sml2.sm)
   SECTIONS
   {
#if defined(__WORKAROUND_AVOID_LDF_BLOCK_BOUNDARIES) /* { */
    /* Workaround for hardware errata 05-00-0189 -
    ** "Speculative (and fetches made at boundary of reserved memory
    ** space) for instruction or data fetches may cause false
    ** protection exceptions".
    **
    ** Done by avoiding use of 76 bytes from at the end of blocks
    ** that are adjacent to reserved memory. Workaround is enabled
    ** for appropriate silicon revisions (-si-revision switch).
    */
//    RESERVE(___wab7=0xFEB1FFFF - 75,___l7=76)     /* L2 sram */
    RESERVE(___wab8=0x2FFFFFFF - 75,___l8=76)     /* async bank 3 */
#  if defined(PARTITION_EZKIT_SDRAM)
    RESERVE(___wab9=0x3FFFFFF - 75,___l9=76)      /* EZ-Kit sdram */
#  elif defined(USE_CACHE) || defined(USE_SDRAM)
    RESERVE(___wab10=0x7FFFFFF - 75,___l10=76)    /* sdram */
#  endif
#else
    /* FEB1FC00->FEB1FFFF : Reseved in boot Phase for 2nd stage boot loader */
    RESERVE(___ssld=0xFEB1FC00,___lssld=0x400)
#endif /*} __WORKAROUND_AVOID_LDF_BLOCK_BOUNDARIES */

        l2_sram
        {
            INPUT_SECTION_ALIGN(4)
            INPUT_SECTIONS( $OBJECTS(l2_sram) $LIBRARIES_SML2(l2_sram))
#if defined(__ADI_MULTICORE)
            INPUT_SECTIONS( $OBJECTS(mc_data) $LIBRARIES_SML2(mc_data))
#endif
            // Holds control variable used to ensure atomic file I/O
            // Must be in shared memory and NOT cached.
            INPUT_SECTIONS( $LIBRARIES_SML2(primio_atomic_lock))

            INPUT_SECTIONS( $LIBRARIES_SML2(noncache_code))
            INPUT_SECTIONS( $LIBRARIES_SML2(program))
            INPUT_SECTIONS( $LIBRARIES_SML2(data1))
            INPUT_SECTIONS( $LIBRARIES_SML2(constdata))
            INPUT_SECTIONS( $OBJECTS(voldata) $LIBRARIES_SML2(voldata))
        } >MEM_L2_SRAM

        l2_bsz ZERO_INIT
        {
            INPUT_SECTION_ALIGN(4)
            INPUT_SECTIONS( $LIBRARIES_SML2(bsz))
        } >MEM_L2_SRAM

        sdram0_bank1 {               // Data
          INPUT_SECTION_ALIGN(4)
          INPUT_SECTIONS($OBJECTS(sdram_data) $LIBRARIES_SML3(sdram_data))
          INPUT_SECTIONS($LIBRARIES_SML3(data1))
          INPUT_SECTIONS($LIBRARIES_SML3(voldata))
        } >MEM_SDRAM0_BANK1

        sdram0_bank2 {               // Data
          INPUT_SECTION_ALIGN(4)
          INPUT_SECTIONS($OBJECTS(sdram0) $LIBRARIES_SML3(sdram0))
          INPUT_SECTIONS($LIBRARIES_SML3(constdata))
          INPUT_SECTIONS($LIBRARIES_SML2(bsz_init) $LIBRARIES_SML3(bsz_init))
        } > MEM_SDRAM0_BANK2

        sdram0_bank2_bsz ZERO_INIT { // Bsz
          INPUT_SECTION_ALIGN(4)
          INPUT_SECTIONS($LIBRARIES_SML3(bsz))
        } > MEM_SDRAM0_BANK2

        .meminit { ALIGN(4) } >MEM_SDRAM0_BANK2

        sdram0_bank3 {               // Program Section
          INPUT_SECTION_ALIGN(4)
          INPUT_SECTIONS($LIBRARIES_SML3(program))
          INPUT_SECTIONS($LIBRARIES_SML3(noncache_code))
        } >MEM_SDRAM0_BANK3

#if defined(__ADI_MULTICORE)
        heap {                      // Allocate a heap for the application
            ldf_heap_space = .;
            ldf_heap_end = ldf_heap_space + MEMORY_SIZEOF(MEM_SDRAM0_HEAP) - 1;
            ldf_heap_length = ldf_heap_end - ldf_heap_space;
        } >MEM_SDRAM0_HEAP
#endif
   }
}

/* Core A */
PROCESSOR p0
{
MEMORY
{
/* ----- Core A ----- */
//MEM_A_L1_SCRATCH {	/* L1 Scratchpad - 4K */
//	TYPE(RAM) WIDTH(8)
//	START(0xFFB00000) END(0xFFB00FFF)
//}
MEM_A_L1_CODE_CACHE  {	/* Instruction SRAM/Cache - 16K */
	TYPE(RAM) WIDTH(8)
	START(0xFFA10000) END(0xFFA13FFF)
}
MEM_A_L1_CODE {		/* Instruction SRAM - 16K */
	TYPE(RAM) WIDTH(8)
	START(0xFFA00000) END(0xFFA03FFF)
}
#if DATAB_CACHE /* { */
MEM_A_L1_DATA_B_CACHE {	/* Data Bank B SRAM/Cache - 16K */
	TYPE(RAM) WIDTH(8)
	START(0xFF904000) END(0xFF907FFF)
}
MEM_A_L1_DATA_B   {		/* Data Bank B SRAM - 12K of 16K */
	TYPE(RAM) WIDTH(8)
	START(0xFF901000) END(0xFF903FFF)
}
#else  /* } { DATAB_CACHE */
MEM_A_L1_DATA_B   {		/* Data Bank B SRAM - 28K of 32K */
	TYPE(RAM) WIDTH(8)
	START(0xFF901000) END(0xFF907FFF)
}
#endif /* } DATAB_CACHE */
MEM_A_L1_STACK    {		/* Data Bank B SRAM - 4K of 16K */
	TYPE(RAM) WIDTH(8)
	START(0xFF900000) END(0xFF900FFF)
}
#if DATAA_CACHE /* { */
MEM_A_L1_DATA_A_CACHE {	/* Data Bank A SRAM/Cache - 16K */
	TYPE(RAM) WIDTH(8)
	START(0xFF804000) END(0xFF807FFF)
}
MEM_A_L1_DATA_A   {		/* Data Bank A SRAM - 16K */
	TYPE(RAM) WIDTH(8)
	START(0xFF800000) END(0xFF803FFF)
}
#else  /* } { DATAA_CACHE */
MEM_A_L1_DATA_A   {		/* Data Bank A SRAM - 16K */
	TYPE(RAM) WIDTH(8)
	START(0xFF800000) END(0xFF807FFF)
}
#endif /* } DATAA_CACHE */
}
    OUTPUT( $COMMAND_LINE_OUTPUT_DIRECTORY/p0.dxe )

	/* Following address must match start of MEM_A_L1_CODE */
	RESOLVE(start,0xFFA00000)
	KEEP(start,_main)
	LINK_AGAINST($COMMAND_LINE_OUTPUT_DIRECTORY/sml2.sm)

   SECTIONS
   {
#if defined(__WORKAROUND_AVOID_LDF_BLOCK_BOUNDARIES) /* { */
    /* Workaround for hardware errata 05-00-0189 -
    ** "Speculative (and fetches made at boundary of reserved memory
    ** space) for instruction or data fetches may cause false
    ** protection exceptions".
    **
    ** Done by avoiding use of 76 bytes from at the end of blocks
    ** that are adjacent to reserved memory. Workaround is enabled
    ** for appropriate silicon revisions (-si-revision switch).
    */
//    RESERVE(___waba0=0xFFB00FFF - 75,___la0=76)   /* scratchpad */
#  if !INSTR_CACHE
    RESERVE(___waba1=0xFFA13FFF - 75,___la1=76)   /* l1 instr sram/cache */
#  endif
    RESERVE(___waba2=0xFFA03FFF - 75,___la2=76)   /* l1 instr sram */
#  if DATAB_CACHE
    RESERVE(___waba3=0xFF903FFF - 75,___la3=76)   /* data B sram */
#  else
    RESERVE(___waba4=0xFF907FFF - 75,___la4=76)   /* data B sram/cache */
#  endif
#  if DATAA_CACHE
    RESERVE(___waba5=0xFF803FFF - 75,___la5=76)   /* data A sram */
#  else
    RESERVE(___waba6=0xFF807FFF - 75,___la6=76)   /* data A sram/cache */
#  endif
#endif /*} __WORKAROUND_AVOID_LDF_BLOCK_BOUNDARIES */

        l1_code
        {
            INPUT_SECTION_ALIGN(4)
            __CORE = 0;
            INPUT_SECTIONS( $OBJECTS_CORE_A(L1_code) $LIBRARIES_CORE_A(L1_code))
            INPUT_SECTIONS( $OBJECTS_CORE_A(cplb) $LIBRARIES_CORE_A(cplb))
            INPUT_SECTIONS( $OBJECTS_CORE_A(cplb_code) $LIBRARIES_CORE_A(cplb_code))
            INPUT_SECTIONS( $OBJECTS_CORE_A(noncache_code) $LIBRARIES_CORE_A(noncache_code))
            INPUT_SECTIONS( $OBJECTS_CORE_A(program) $LIBRARIES_CORE_A(program))
        } >MEM_A_L1_CODE

        l1_code_cache
        {
#if INSTR_CACHE /* { */
            ___l1_code_cache = 1;
#else
            ___l1_code_cache = 0;
            INPUT_SECTION_ALIGN(4)
            INPUT_SECTIONS( $OBJECTS_CORE_A(L1_code) $LIBRARIES_CORE_A(L1_code))
            INPUT_SECTIONS( $OBJECTS_CORE_A(cplb) $LIBRARIES_CORE_A(cplb))
            INPUT_SECTIONS( $OBJECTS_CORE_A(cplb_code) $LIBRARIES_CORE_A(cplb_code))
            INPUT_SECTIONS( $OBJECTS_CORE_A(program) $LIBRARIES_CORE_A(program))
#endif /* INSTR_CACHE } */
        } >MEM_A_L1_CODE_CACHE

#if DATAA_CACHE /* { */
        l1_data_a_cache
        {
            INPUT_SECTION_ALIGN(4)
            ___l1_data_cache_a = 1;
        } >MEM_A_L1_DATA_A_CACHE
#endif /* DATAA_CACHE } */

        l1_data_a
        {
            INPUT_SECTION_ALIGN(4)
#if !DATAA_CACHE /* { */