confphy5.inc

keilc pic的版本 才搞到的 希望对大家有帮助

;
; Definitions for SYSCON and BUSCON0 Register:
; --------------------------------------------
;
; MCTC0: Memory Cycle Time (BUSCON0.0 .. BUSCON0.3):
; Note: if RDYEN0 == 1 a maximum number of 7 waitstates can be selected
_MCTC0	 EQU	2	; Memory wait states is 1 (MCTC0 = 0EH).
;			; (Reset Value = 15 additional state times)
;
; RWDC0: Read/Write Signal Delay (BUSCON0.4):
_RWDC0	 EQU	1	; 0 = Delay Time     0.5 States (Reset Value)  
;			; 1 = No Delay Time  0   States
;
; MTTC0: Memory Tri-state Time (BUSCON0.5):
_MTTC0	 EQU	0	; 0 = Delay Time     0.5 States (Reset Value)
;			; 1 = No Delay Time  0   States
;
$SET (BTYP_ENABLE = 0)  ; 0 = BTYP0 and BUSACT0 is set according to the level
                        ;     at pins P0L.6 and P0L.7 during reset.
			; 1 = the following _BTYP0 and _BUSACT0 values are
			;     written to BTYP0 and BUSACT0

; BTYP0: External Bus Configuration Control (BUSCON.6 .. BUSCON.7):
_BTYP0	 EQU	2	; 0 = 8 Bit Non Multiplexed
;			; 1 = 8 Bit Multiplexed
;			; 2 = 16 Bit Non Multiplexed
;			; 3 = 16 Bit Multiplexed
;
; ALECTL0: ALE Lengthening Control Bit (BUSCON0.9):
_ALECTL0 EQU	0	; see data sheet for description
;
; BUSACT0: Bus Active Control Bit (BUSCON0.10):
_BUSACT0 EQU	1	; = 0 external bus disabled
			; = 1 external bus enabled
;
; RDYEN0: READY# Input Enable control bit (BUSCON0.12):
_RDYEN0  EQU	0	; 0 = READY# function disabled  (Reset Value)
;			; 1 = READY# function enabled
;
; RDY_AS: Synchronous / Asynchronous READY# Input (BUSCON.3):
; Note: This bit is only valid if _RDYEN == 1.
_RDY_AS EQU	0	; 0 = synchronous READY# input
;			; 1 = asynchronous READY# input
;
; WRCFG: Write Configuration Control Bit (SYSCON.7):
_WRCFG	 EQU	1	; 0 = Normal configuration of WR# and BHE#
;			; 1 = WR# pin acts as WRL#, BHE# pin acts as WRH#

; CLKEN: System Clock Output Enable bit (SYSCON.8):
_CLKEN	EQU	0	; 0 = disabled    (Reset Value)
;			; 1 = enabled
;
; BYTDIS: Byte High Enable pin control bit (SYSCON.9):
_BYTDIS	EQU	0	; 0 = enabled     (Reset Value)
;			; 1 = disabled
;
; ROMEN: Internal ROM Access Enable is read only (SYSCON.10):
_ROMEN	EQU	0	; 0 = Internal ROM disabled
			; 1 = Internal ROM enabled
;
; SGTEN: Segmentation Disable control bit (SYSCON.11):
_SGTDIS	EQU	0	; 0 = Segmentation enabled (Reset Value)
			; 1 = Segmentation disabled
;
; ROMS1: ROM Segment Mapping Control Bit (SYSCON.12):
_ROMS1  EQU	0	; _ROMS1 = 0 Internal ROM mapped to segment 0
;			; _ROMS1 = 1 Internal ROM mapped to segment 1
;
; STKSZ: Maximum System Stack Size selection  (SYSCON.13 .. SYSCON.15)
_STKSZ	EQU	0	; System stack sizes
; 			; 0 = 256 words (Reset Value)
;			; 1 = 128 words
;			; 2 =  64 words
;			; 3 =  32 words
;                       ; 4 = 512 words
;                       ; 5 = not implemented
;                       ; 6 = not implemented
;                       ; 7 = no wrapping (entire internal RAM use as STACK)
;
;-----------------------------------------------------------------------------
; BOOT960 = 0 : 80C167 CPU with 32 Byte Bootstrap loader is used
; BOOT960 = 1 : 80C167 CPU with 960 Byte Bootstrap loader is used
;
$SET (BOOT960 = 0)
;
;-----------------------------------------------------------------------------
;
; WATCHDOG is always disabled when using MONITOR!
; 
;------------------------------------------------------------------------------


BCON0L		SET     (_MTTC0 << 5) OR (_RWDC0 << 4)
BCON0L		SET	BCON0L OR ((NOT _MCTC0) AND 0FH)
BCON0L		SET	BCON0L AND (NOT (_RDYEN0 << 3))
BCON0L		SET	BCON0L OR (_RDY_AS << 3)
BCON0H		SET	(_ALECTL0 << 1) OR (_RDYEN0 << 4)
$IF (BTYP_ENABLE == 1)
BCON0L		SET	BCON0L OR (_BTYP0 << 6)
BCON0H		SET	BCON0H OR (_BUSACT0 << 2)
$ENDIF

SYS_H		SET	(_STKSZ << 5) OR (_ROMS1 << 4) OR (_SGTDIS << 3)
SYS_H		SET	SYS_H OR (_ROMEN << 2) OR (_BYTDIS << 1) OR _CLKEN
SYS_L		SET	(_WRCFG << 7)