start164.a66

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$MOD167					; Define C167 mode
;
;------------------------------------------------------------------------------
;  This file is part of the C166 Compiler package
;  Copyright KEIL ELEKTRONIK GmbH 1993-1997
;  Version 3.1
;------------------------------------------------------------------------------
;  START164.A66:  This code is executed after processor reset and provides
;                 the startup sequence for the C164 processor.
;
;  To translate this file use A166 with the following invocation:
;
;     A166 START164.A66 SET (<model>)
;
;     <model> determines the memory model and can be one of the following:
;         TINY, SMALL, COMPACT, HCOMPACT, MEDIUM, LARGE or HLARGE
;
;  Example:  A166 START164.A66 SET (SMALL)
;
;  To link the modified START164.OBJ file to your application use the following
;  L166 invocation:
;
;     L166 <your object file list>, START164.OBJ <controls>
;
;------------------------------------------------------------------------------
; Setup model-dependend Assembler controls
$CASE
$IF NOT TINY
$SEGMENTED
$ENDIF
;------------------------------------------------------------------------------
;
; Definitions for BUSCON0 and SYSCON Register:
; --------------------------------------------
;
; MCTC0: Memory Cycle Time (BUSCON0.0 .. BUSCON0.3):
; Note: if RDYEN0 == 1 a maximum number of 7 waitstates can be selected
_MCTC0	 EQU	2	; Memory wait states is 1 (MCTC0 field = 0EH).
;			; (Reset Value = 15 additional state times)
;
; RWDC0: Read/Write Signal Delay (BUSCON0.4):
_RWDC0	 EQU	1	; 0 = Delay Time     0.5 States (Reset Value)  
;			; 1 = No Delay Time  0   States
;
; MTTC0: Memory Tri-state Time (BUSCON0.5):
_MTTC0	 EQU	0	; 0 = Delay Time     0.5 States (Reset Value)
;			; 1 = No Delay Time  0   States
;
$SET (BTYP_ENABLE = 0)  ; 0 = BTYP0 and BUSACT0 is set according to the level
                        ;     at pins P0L.6 and P0L.7 during reset.
			; 1 = the following _BTYP0 and _BUSACT0 values are
			;     written to BTYP0 and BUSACT0
;
; BTYP0: External Bus Configuration Control (BUSCON0.6 .. BUSCON0.7):
_BTYP0	 EQU	3	; 0 = 8 Bit Non Multiplexed
;			; 1 = 8 Bit Multiplexed
;			; 2 = 16 Bit Non Multiplexed
;			; 3 = 16 Bit Multiplexed
;
; ALECTL0: ALE Lengthening Control Bit (BUSCON0.9):
_ALECTL0 EQU	0	; see data sheet for description
;
; BUSACT0: Bus Active Control Bit (BUSCON0.10):
_BUSACT0 EQU	1	; = 0 external bus disabled
			; = 1 external bus enabled
;
; RDYEN0: READY# Input Enable control bit (BUSCON0.12):
_RDYEN0  EQU	0	; 0 = READY# function disabled  (Reset Value)
;			; 1 = READY# function enabled
;
; RDY_AS0: Synchronous / Asynchronous READY# Input (BUSCON0.3):
; Note: This bit is only valid if _RDYEN0 == 1.
_RDY_AS0 EQU	0	; 0 = synchronous READY# input
;			; 1 = asynchronous READY# input
;
; Note: The control bits XPER-SHARE (SYSCON.0) and VISIBLE (SYSCON.1) are
; implemented primarily for debugging support and are not altered during
; the C166 startup code.  If you want to set this bits explicit, you must
; change the BFLDL SYSCON instruction in the code below.
;
; XRAMEN: XRAM Enable Control Bit (SYSCON.2)
_XRAMEN	EQU	1	; 0 = access to on-chip XRAM disable, ext. bus access
;                       ; 1 = on-chip XRAM is accessed
;
$SET (WRCFG_ENABLE = 0) ; 0 = WRCFG is set according to the level at
                        ;     pin P0H.0 during reset.
			; 1 = the following _WRCFG value is
			;     written to WRCFG in the SYSCON register
; WRCFG: Write Configuration Control Bit (SYSCON.7):
_WRCFG	 EQU	1	; 0 = Normal configuration of WR# and BHE#
;			; 1 = WR# pin acts as WRL#, BHE# pin acts as WRH#
;
; CLKEN: System Clock Output Enable bit (SYSCON.8):
_CLKEN	EQU	0	; 0 = disabled    (Reset Value)
;			; 1 = enabled
;
; BYTDIS: Byte High Enable pin control bit (SYSCON.9):
_BYTDIS	EQU	0	; 0 = enabled     (Reset Value)
;			; 1 = disabled
;
; ROMEN: Internal ROM Access Enable is read only (SYSCON.10):
_ROMEN	EQU	0	; 0 = Internal ROM disabled
			; 1 = Internal ROM enabled
;
; SGTDIS: Segmentation Disable control bit (SYSCON.11):
$IF TINY
_SGTDIS	EQU	1	; disable segmented mode for TINY model
$ELSE
_SGTDIS	EQU	0	; enable segmented mode (Reset Value)
$ENDIF
;
; ROMS1: ROM Segment Mapping Control Bit (SYSCON.12):
_ROMS1  EQU	0	; _ROMS1 = 0 Internal ROM mapped to segment 0
;			; _ROMS1 = 1 Internal ROM mapped to segment 1
;
; STKSZ: Maximum System Stack Size selection  (SYSCON.13 .. SYSCON.15)
;  Defines the system stack space which is used by CALL/RET and PUSH/POP
;  instructions.  The system stack space must be adjusted according the
;  actual requirements of the application.
$SET (STK_SIZE = 0)
;     System stack sizes:
;       0 = 256 words (Reset Value)
;       1 = 128 words
;       2 =  64 words
;       3 =  32 words
;       4 = 512 words
;       5 = not implemented
;       6 = not implemented
;       7 = no wrapping (entire internal RAM use as STACK, set size with SYSSZ)
; If you have selected 7 for STK_SIZE, you can set the actual system stack size
; with the following SSTSZ statement.
SSTSZ	EQU	200H	; set System Stack Size to 200H Bytes
;
; USTSZ: User Stack Size Definition 
;  Defines the user stack space available for automatics.  This stack space is
;  accessed by R0.  The user stack space must be adjusted according the actual
;  requirements of the application.
USTSZ	EQU	1000H	; set User Stack Size to 1000H Bytes.
;
; WATCHDOG: Disable Hardware Watchdog
; --- Set WATCHDOG = 1 to enable the Hardware watchdog
$SET (WATCHDOG = 0)
;
;
; CLR_MEMORY: Disable Memory Zero Initialization of RAM area
; --- Set CLR_MEMORY = 0 to disable memory zero initilization
$SET (CLR_MEMORY = 1)
;
; INIT_VARS: Disable Variable Initialization
; --- Set INIT_VARS = 0 to disable variable initilization
$SET (INIT_VARS = 1)
;
; DPPUSE:  Re-assign DPP registers
; --- Set DPPUSE = 0 to reduce the code size of the startup code, if you
;                    are not using the L166 DPPUSE directive.
$SET (DPPUSE = 1)
;
;------------------------------------------------------------------------------
;
; Initialization for SYSCON2 and SYSCON3 (available on some derivatives only)
;
; ADVANCED_SYSCON: Init SYSCON2 and SYSCON3 register available on some devices
; --- Set ADVANCE_SYSCON = 1 to initilize SYSCON2 and SYSCON3
$SET (ADVANCED_SYSCON = 0)
;
; --- SYSCON2 values
;
; PDCON: Power Down Control (during power down mode) (SYSCON2.4 .. SYSCON2.5)
PDCON   EQU     0       ; 0 = RTC On,  Ports On  (default after Reset)
;                       ; 1 = RTC On,  Ports Off
;                       ; 2 = RTC Off, Ports On
;                       ; 3 = RTC Off, Ports Off
;
; RTC: RTC Clock Source (not affected by a reset) (SYSCON2.6)
RTC     EQU     0	; 0 = Main oscillator
;                       ; 1 = Auxiliary oscillator (if available)
;
; SCS: SDD Clock Source (not affected by a reset) (SYSCON2.7)
SCS     EQU     0	; 0 = Main oscillator
;                       ; 1 = Auxiliary oscillator (if available)
;
; CLKCON: Clock State Control (SYSCON2.8 .. SYSCON2.9)
CLKCON  EQU     0	; 0 = Running on configured basic frequency
;                       ; 1 = Running on slow down frequency, PLL ON
;                       ; 2 = Running on slow down frequency, PLL OFF
;                       ; 3 = reserved
;
; CLKREL: Reload Counter Value for Slowdown Devider (SYSCON2.10 .. SYSCON2.14)
CLKREL  EQU     0       ; possible values are 0 .. 31
;
;
; --- SYSCON3 values: disable on-chip peripherals
;
ADCDIS  EQU     0       ; 1 = disable Analog/Digital Converter    (SYSCON3.0)
ASC0DIS EQU	0	; 1 = disable UART ASC0                   (SYSCON3.1)
SSCDIS	EQU	0	; 1 = disable Synchronus Serial Cnl SSC   (SYSCON3.2)
GPT1DIS	EQU	0	; 1 = disable Timer Block GPT1            (SYSCON3.3)
GPT2DIS	EQU	0	; 1 = disable Timer Block GPT2            (SYSCON3.4)
FMDIS 	EQU	0	; 1 = disable on-chip Flash Memory Module (SYSCON3.5)
CC1DIS	EQU	0	; 1 = disable CAPCOM Unit 1               (SYSCON3.6)
CC2DIS	EQU	0	; 1 = disable CAPCOM Unit 2               (SYSCON3.7)
CC6DIS	EQU	0	; 1 = disable CAPCOM Unit 6               (SYSCON3.8)
PWMDIS	EQU	0	; 1 = disable Pulse Width Modulation Unit (SYSCON3.9)
ASC1DIS EQU	0	; 1 = disable UART ASC1                   (SYSCON3.10)
I2CDIS  EQU     0       ; 1 = disable I2C Bus Module              (SYSCON3.11)
;                       ; reserved                                (SYSCON3.12)
CAN1DIS EQU     0       ; 1 = disable on-chip CAN Module 1        (SYSCON3.13)
CAN2DIS EQU     0       ; 1 = disable on-chip CAN Module 2        (SYSCON3.14)
PCDDIS  EQU     0       ; 1 = disable Peripheral Clock Driver     (SYSCON3.15)
;
;------------------------------------------------------------------------------
;
; BUSCON1/ADDRSEL1  Initialization
; =================================
;
;
; BUSCON1/ADDRSEL1
; --- Set BUSCON1 = 1 to initialize the BUSCON1/ADDRSEL1 registers
$SET (BUSCON1 = 0)
;
; Define the start address and the address range of Chip Select 1 (CS1#) 
; This values are used to set the ADDRSEL1 register
%DEFINE (ADDRESS1) (00000H)     ; Set CS1# Start Address (default 00000H)
%DEFINE (RANGE1)   (512K)      ; Set CS1# Range (default 512K = 512KB)
;  
; MCTC1: Memory Cycle Time (BUSCON1.0 .. BUSCON1.3):
; Note: if RDYEN1 == 1 a maximum number of 7 waitstates can be selected
_MCTC1	 EQU	1	; Memory wait states is 1 (MCTC1 field = 0EH).
;
; RWDC1: Read/Write Signal Delay (BUSCON1.4):
_RWDC1	 EQU	0	; 0 = Delay Time     0.5 States
;			; 1 = No Delay Time  0   States
;
; MTTC1: Memory Tri-state Time (BUSCON1.5):
_MTTC1	 EQU	1	; 0 = Delay Time     0.5 States
;			; 1 = No Delay Time  0   States
;
; BTYP1: External Bus Configuration Control (BUSCON1.6 .. BUSCON1.7):
_BTYP1	 EQU	2	; 0 = 8 Bit Non Multiplexed
;			; 1 = 8 Bit Multiplexed
;			; 2 = 16 Bit Non Multiplexed
;			; 3 = 16 Bit Multiplexed
;
; ALECTL1: ALE Lengthening Control Bit (BUSCON1.9):
_ALECTL1 EQU	0	; see data sheet for description
;
; BUSACT1: Bus Active Control Bit (BUSCON1.10):
_BUSACT1 EQU	1	; = 0 external (ADDRSEL1) bus disabled
			; = 1 external (ADDRSEL1) bus enabled
;
; RDYEN1: READY# Input Enable control bit (BUSCON1.12):
_RDYEN1  EQU	0	; 0 = READY# function disabled
;			; 1 = READY# function enabled
;
; RDY_AS1: Synchronous / Asynchronous READY# Input (BUSCON1.3):
; Note: This bit is only valid if _RDYEN1 == 1.
_RDY_AS1 EQU	0	; 0 = synchronous READY# input
;			; 1 = asynchronous READY# input
;
; CSREN1: Read Chip Select Enable bit (BUSCON1.14):
_CSREN1  EQU	0	; 0 = CS1# is independent of read command (RD#)
;			; 1 = CS1# is generated for the duration of read
;
; CSWEN1: Read Chip Select Enable bit (BUSCON1.15):
_CSWEN1  EQU	0	; 0 = CS1# is independent of write command (RD#)
;			; 1 = CS1# is generated for the duration of write
;
;------------------------------------------------------------------------------

$IF TINY
$SET (DPPUSE = 0)
$ENDIF

_STKSZ		SET	0
_STKSZ1		SET	0		; size is 512 Words
$IF (STK_SIZE = 0)
_STKSZ1		SET	1		; size is 256 Words
$ENDIF
$IF (STK_SIZE = 1)
_STKSZ		SET	1
_STKSZ1		SET	2		; size is 128 Words
$ENDIF
$IF (STK_SIZE = 2)
_STKSZ		SET	2
_STKSZ1		SET	3		; size is  64 Words
$ENDIF
$IF (STK_SIZE = 3)
_STKSZ		SET	3
_STKSZ1		SET	4		; size is  32 Words
$ENDIF
$IF (STK_SIZE = 4)
_STKSZ		SET	4
$ENDIF
$IF (STK_SIZE = 5)
_STKSZ		SET	5
$ENDIF
$IF (STK_SIZE = 6)
_STKSZ		SET	6
$ENDIF
$IF (STK_SIZE = 7)
_STKSZ		SET	7
$ENDIF


$IF NOT TINY
ASSUME	DPP3:SYSTEM
ASSUME  DPP2:NDATA
$ENDIF

NAME	?C_STARTUP
PUBLIC	?C_STARTUP

$IF MEDIUM OR LARGE OR HLARGE
Model	LIT	'FAR'
$ELSE
Model	LIT	'NEAR'
$ENDIF

EXTRN	main:Model

PUBLIC		?C_USRSTKBOT

?C_USERSTACK	SECTION	DATA PUBLIC 'NDATA'
$IF NOT TINY
NDATA		DGROUP	?C_USERSTACK
$ENDIF
?C_USRSTKBOT:
		DS	USTSZ		; Size of User Stack
?C_USERSTKTOP:
?C_USERSTACK	ENDS

?C_MAINREGISTERS	REGDEF	R0 - R15

$IF (STK_SIZE = 7)

?C_SYSSTACK	SECTION	DATA PUBLIC 'IDATA'
$IF NOT TINY
SDATA		DGROUP	?C_SYSSTACK
$ENDIF
_BOS:					; bottom of system stack
		DS	SSTSZ		; Size of User Stack
_TOS:					; top of system stack
?C_SYSSTACK	ENDS

$ELSE
; Setup Stack Overflow
_TOS	EQU	0FC00H			        ; top of system stack
_BOS	EQU	_TOS - (1024 >> _STKSZ1)	; bottom of system stack
$ENDIF

PUBLIC		?C_SYSSTKBOT
?C_SYSSTKBOT	EQU	_BOS

		SSKDEF	_STKSZ		; System stack size

?C_STARTUP_CODE	SECTION	CODE	'ICODE'


;------------------------------------------------------------------------------

; Special Function Register Addresses
SYSCON   DEFR   0FF12H
BUSCON0  DEFR   0FF0CH
SP       DEFR	0FE12H
STKOV    DEFR   0FE14H
STKUN    DEFR	0FE16H
P3       DEFR	0FFC4H
DP3      DEFR	0FFC6H
BUSCON1  DEFR   0FF14H
ADDRSEL1 DEFR   0FE18H
SYSCON2  DEFR   0F1D0H
SYSCON3  DEFR   0F1D4H

%*DEFINE (ADDR (Val, Start, Range)) (
%SET (adr, %SUBSTR(%Start,1,(%LEN(%Start)- 3))%SUBSTR(%Start,%LEN(%Start),1))
%IF (%EQS (%Range,4K))     THEN (%SET (adr, (%adr AND 0FFF0H) + 0)) FI
%IF (%EQS (%Range,8K))     THEN (%SET (adr, (%adr AND 0FFE0H) + 1)) FI
%IF (%EQS (%Range,16K))    THEN (%SET (adr, (%adr AND 0FFC0H) + 2)) FI